User manual MSI G52-75121X1 V1.0

[. . . ] P45 Platinum Series MS-7512 (v1. X) Mainboard G52-75121X1 i Copyright Notice T he material in this doc ument is the intellec tual property of M ICRO-STAR INTERNATIONAL. We take every care in the preparation of this document, but no guarantee is given as to the correctness of its contents. Our products are under continual improvement and we reserve the right to make changes without notice. Trademarks All trademarks are the properties of their respective owners. NVIDIA, the NVIDIA logo, DualNet, and nForce are registered trademarks or trademarks of NVIDIA Corporation in the United States and/or other countries. [. . . ] tRP W hen the Configuration DRAM Timing by SPD sets to [Manual], the field is adjustable. This item controls the number of cycles for Row Address Strobe (RAS) to be allowed to precharge. If insufficient time is allowed for the RAS to accumulate its charge before DRAM refresh, refreshing may be incomplete and DRAM may fail to retain data. This item applies only when synchronous DRAM is installed in the system. tRAS W hen the Configuration DRAM Timing by SPD sets to [Manual], the field is adjustable. This setting determines the time RAS takes to read from and write to a memory cell. tRFC W hen the Configuration DRAM Timing by SPD sets to [Manual], this setting determines the time RFC takes to read from and write to a memory cell. 3-20 BIOS Setup tWR W hen the Configuration DRAM Timing by SPD is set to [Manual], the field is adjustable. It specifies the amount of delay (in clock cycles) that must elapse after the completion of a valid write operation, before an active bank can be precharged. This delay is required to guarantee that data in the write buffers can be written to the memory cells before precharge occurs. tWTR W hen the Configuration DRAM Timing by SPD is set to [Manual], the field is adjustable. This item controls the W rite Data In to Read Command Delay memory timing. This constitutes the minimum number of clock cycles that must occur between the last valid write operation and the next read command to the same internal bank of the DDR device. tRRD W hen the Configuration DRAM Timing by SPD sets to [Manual], the field is adjustable. Specifies the active-to-active delay of different banks. tRTP W hen the Configuration DRAM Timing by SPD sets to [Manual], time interval between a read and a precharge command. MEMORY-Z Press <Enter> to enter the sub-menu and the following screen appears. DIM M1/2/3/4 Memory SPD Information Press <Enter> to enter the sub-menu and the following screen appears. DIM M 1/ 2/ 3/ 4 M e mo ry S PD Information These items display the current status of the current DIMM Memory speed information suc h as momory type, max bandwidth, manufacture, part number, serial number, SDRAM cycle time, DRAM TCL, DRAM TRCD, DRAM TRP, DRAM TRAS, DRAM TRFC, DRAM TWR, DRAM TWTR, DRAM TRRD and DRAM TRTP. They are read only. 3-21 M S-7512 M ainboard FSB/DRAM Ratio This item will allow you to adjust the FSB/Ratio of the memory. Adjusted DDR M emory Frequency It shows the adjusted DDR Memory frequency. Adjust PCI Frequency (MHz) This field allows you to select the PCIE frequency (in MHz). Auto Disable DRAM /PCI Frequency W hen set to [Enabled], the system will remove (turn off) clocks from empty DIMM and PCI slots to minimize the electromagnetic interference (EMI). CPU Voltage (V) / CPU GTL REF0 / CPU GTL REF1 / DRAM Voltage (V) / DDR_VREF_A / DDR_VREF_B / NB Voltage (V) / NB GTL REF / VTT FSB Voltage / SB Voltage (V) These items dispaly the power status of Memory, FSB and chipset. [. . . ] From W indows Vista/XP, open the Control Panel from My Computer followed by the System icon. Choose the Hardware tab, then click the Device M anager tab. Click the "+" in front of the SCSI and RAID Controllers hardware type. The driver JMicron JM B36X Controller should appear. D-12 JMicron RAID JMicron Raid Configurer There is an application called JMRaidTool which helps you perform the following tasks of JMicron RAID. [. . . ]