User manual OMRON CP1L

[. . . ] W471-E1-04 SYSMAC CP Series CP1L-J_D_ CP1L-L_D_ CP1L-M_D_ CP1L CPU Unit OPERATION MANUAL CP1L-J14D@-@ CP1L-J20D@-@ CP1L-L10D@-@ CP1L-L14D@-@ CP1L-L20D@-@ CP1L-M30D@-@ CP1L-M40D@-@ CP1L-M60D@-@ CP1L CPU Unit Operation Manual Revised August 2008 iv Notice: OMRON products are manufactured for use according to proper procedures by a qualified operator and only for the purposes described in this manual. The following conventions are used to indicate and classify precautions in this manual. Always heed the information provided with them. Failure to heed precautions can result in injury to people or damage to property. !DANGER !WARNING !Caution Indicates an imminently hazardous situation which, if not avoided, will result in death or serious injury. [. . . ] Note Memory Cassette cannot be used in CP1L-J CPU Unit. Use the following Memory Cassette. Model CP1W-ME05M Specifications · Memory size 512 Kwords · Storage capacity The following CPU Unit data (for each Unit) · User programs · Parameters · Comment memory · Function Block (FB) sources · DM initial values in the built-in flash memory · DM in RAM · Write method · Read method Operations from the CX-Programmer Powering up with DIP switch pin SW2 set to ON, or operations from the CX-Programmer Memory Cassette Specifications 396 Memory Cassette Functions Data that Can be Stored on a Memory Cassette The following data can be stored on a Memory Cassette. Data stored on Memory Cassette User programs Parameters Comment data for user programs Section 6-6 Location in CPU Unit Built-in RAM, built-in flash memory (User Program Area) PLC Setup, CPU Bus Unit set- Built-in RAM, built-in flash tings, routing tables memory (Parameter Area) Variable tables Built-in flash memory (Comment Memory Area) (I/O comments, rung comBuilt-in flash memory (Comments, program comments) ment Memory Area) Built-in flash memory (Comment Memory Area) Built-in flash memory (FB Source Memory Area) Built-in RAM (D0 to D32767 in DM Area) Built-in flash memory (DM Initial Values Area) Program indexes (section names, section comments, program comments) Function Block (FB) sources DM DM initial values (See note. ) The areas for storing various types of data have fixed allocations in the Memory Cassette, and a single Memory Cassette corresponds to a single CPU Unit. Therefore it is not possible to simultaneously store multiple items of the same type of data (e. g. , two user programs). Also, the data can only be read to a CPU Unit. It cannot be directly managed from a personal computer like files. The only data that can be stored on a Memory Cassette is the data from a CPU Unit. Note The CX-Programmer's function for saving DM initial values is used for saving the values in the DM Area (D0 to D32767) to the built-in flash memory as initial values. By means of a setting in the PLC Setup, these initial values can then be automatically written to the DM Area (D0 to D32767) when the power is turned ON. 6-6-2 Mounting and Removing a Memory Cassette 1, 2, 3. . . 1. Turn OFF the power supply to the PLC and removed the cover to the Memory Cassette socket. CPU Units with 10, 14 or 20 I/O Points CPU Units with 30, 40 or 60 I/O Points Mounting 397 Memory Cassette Functions Section 6-6 2. Holding the Memory Cassette with the side with the nameplate facing upwards, insert the Memory Cassette all the way into the slot. CPU Units with 10, 14 or 20 I/O Points CPU Units with 30, 40 or 60 I/O Points MEMORY MEMORY Removal 1, 2, 3. . . 1. Grasp the end of the Memory Cassette between the thumbnail and index finger, and slide it upwards to remove it. CPU Units with 10, 14 or 20 I/O Points CPU Units with 30, 40 or 60 I/O Points MEMORY MEMORY Note (1) Turn OFF the power supply before mounting or removing the Memory Cassette. (2) Absolutely do not remove the Memory Cassette while the BKUP indicator is flashing (i. e. , during a data transfer or verification). Doing so could make the Memory Cassette unusable. (3) The Memory Cassette is small, so be careful to not let it be dropped or lost when it is removed. 398 Memory Cassette Functions Section 6-6 6-6-3 Operation Using the CX-Programmer Use the following procedure for the Memory Cassette function. 1, 2, 3. . . 1. The following Memory Cassette Transfer/Data Memory Backup Dialog Box will be displayed. 2. Under Transfer Data Area, check whatever types of data are to be transferred. Click the Valid Area Check Button to check the valid areas in the Memory Cassette mounted in the CPU Unit and the operating mode after automatic transfer at startup. If the user program is specified to be written, select the operating mode after automatic transfer at startup. · PROGRAM mode (default): Used, e. g. , to copy the system. · Use PLC Setup: Used, e. g. , for operation with the Memory Cassette. Execute any of the following operations. · To write data from the CPU Unit to the Memory Cassette: Click the PLC Memory Cassette Button. [. . . ] Received Bytes: Receive specified number of bytes. CR, LF Set End Code Every cycle Every cycle Every cycle 165 (CP1L Mtype CPU Unit) 164 (CP1L Mtype CPU Unit) 165 (CP1L Mtype CPU Unit) 12 Every cycle 160 (CP1L Mtype CPU Unit) 00 to 03 Every cycle 161 (CP1L Mtype CPU Unit) 00 to 07 01 hex 02 hex 03 hex 04 hex 05 hex 00 or 06 hex 07 hex 08 hex 09 hex 0A hex 0 hex 1 hex 2 hex 4 hex 5 hex 6 hex 8 hex 9 hex A hex C hex D hex E hex 0 1 08 to 15 00 hex : FF hex 08 and 09 00 10 01 705 PLC Setup Name 2 2-3 2-3-6 Received Bytes Default 256 bytes Settings 256 bytes 1 byte : 255 bytes 2-3-7 Set End Code 0x0000 0x0000 : 0x00FF 2-3-8 Delay 0: 0 × 10 ms 0: 0 × 10 ms : 9999: 9999 × 10 ms 2-4 ToolBus (peripheral bus) 2-4-1 Baud 9, 600 bps 9, 600 bps 19, 200 bps 38, 400 bps 57, 600 bps 115, 200 bps 2-5 Serial Gateway 2-5-1 Baud 9, 600 bps 300 bps 600 bps 1, 200 bps 2, 400 bps 4, 800 bps 9, 600 bps 19, 200 bps 38, 400 bps 57, 600 bps 115, 200 bps 2-5-2 Format (data length, stop bits, parity) 7, 2, E: 7-bit data, 2 stop 7, 2, E: 7-bit bits, even parity data, 2 stop bits, even parity 7, 2, O: 7-bit data, 2 stop bits, odd parity 7, 2, N: 7-bit data, 2 stop bits, no parity 7, 1, E: 7-bit data, 2 stop bits, even parity 7, 1, O: 7-bit data, 1 stop bit, odd parity 7, 1, N: 7-bit data, 1 stop bit, no parity 8, 2, E: 8-bit data, 2 stop bits, even parity 8, 2, O: 8-bit data, 2 stop bits, odd parity 8, 2, N: 8-bit data, 2 stop bits, no parity 8, 1, E: 8-bit data, 1 stop bit, even parity 8, 1, O: 8-bit data, 1 stop bit, odd parity 8, 1, N: 8-bit data, 1 stop bit, no parity 2-5-3 Response Timeout 50: 50 × 100 ms = 5s 50: 50 × 100 ms = 5 s 1: 1 × 100 ms : 255: 255 × 100 ms Every cycle 167 (CP1L Mtype CPU Unit) Every cycle 160 (CP1L Mtype CPU Unit) Every cycle 161 (CP1L Mtype CPU Unit) Every cycle 161 (CP1L Mtype CPU Unit) Every cycle Every cycle 164 (CP1L Mtype CPU Unit) 162 (CP1L Mtype CPU Unit) When setting is read by CPU Unit Every cycle Internal address 165 (CP1L Mtype CPU Unit) Appendix G Bits 00 to 07 Settings 00 hex 01 hex : FF hex 00 to 07 00 hex : FF hex 00 to 15 0000 hex : 270F hex 00 to 07 00 or 06 hex 07 hex 08 hex 09 hex 0A hex 00 to 07 01 hex 02 hex 03 hex 04 hex 05 hex 00 or 06 hex 07 hex 08 hex 09 hex 0A hex 00 to 03 0 hex 1 hex 2 hex 4 hex 5 hex 6 hex 8 hex 9 hex A hex C hex D hex E hex 08 to 15 00 hex 01 hex : FF hex 706 PLC Setup Name 2 2-6 PC Link (Slave) 2-6-1 Baud 9, 600 bps (disabled) 38, 400 (standard) 115, 200 (high speed) 0 : 7 2-7 PC Link (Master) 2-7-1 Baud 9, 600 bps (disabled) 38, 400 (standard) 115, 200 (high speed) 1 : 10 (default) ALL Masters Every cycle Every cycle 161 (CP1L Mtype CPU Unit) 166 (CP1L Mtype CPU Unit) 166 (CP1L Mtype CPU Unit) Every cycle Every cycle 161 (CP1L Mtype CPU Unit) 167 (CP1L Mtype CPU Unit) Default Settings When setting is read by CPU Unit Internal address Appendix G Bits Settings 00 to 07 00 hex 0A hex 0 hex : 7 hex 2-6-2 PC Link Unit No. 0 00 to 03 00 to 07 00 hex 0A hex 1 hex : 0 or A hex 0 1 2-7-2 Link Words 10 (default) 04 to 07 2-7-3 PC Link Mode ALL Every cycle 15 707 PLC Setup Appendix G Peripheral Service Settings Set Time to All Events: Time Setting for Services Name 1 Set time to all events Default Default Settings Default (4% of cycle time) Use user setting. 1-1 Time allocated to services 0: 0 × 0. 1 ms = 0 ms 0: 0 × 0. 1 ms = 0 ms : 255: 255 × 0. 1 ms At start of operation 218 00 to 07 When setting is read by CPU Unit At start of operation Internal address 218 Bits 15 0 1 00 hex : FF hex Settings Built-in Input Settings High Speed Counter Settings Name 1 Use high speed counter 0 1-1 Counting mode 1-1-1 Circular Max. Linear mode Circular mode 0 : 4, 294, 967, 295 1-2 Reset Z phase, software reset Z phase, software reset Software reset Z phase, software reset (comparing) Software reset (comparing) 1-3 Input Setting Differential phase input Differential phase input Pulse + direction input Up/Down input Increment pulse input 2 Use high speed counter 1 2-1 Counting mode 2-1-1 Circular Max. [. . . ]