User manual SEAGATE FIREBALL PLUS AS

[. . . ] Quantum Fireball Plus AS 10. 2/20. 5/30. 0/40. 0/60. 0 GB AT Product Manual December 12, 2000 81-121729-04 Quantum reserves the right to make changes and improvements to its products, without incurring any obligation to incorporate such changes or improvements into units previously sold or shipped. You can request Quantum publications from your Quantum Sales Representative or order them directly from Quantum. Publication Number: 81-121729-04 UL/CSA/TUV/CE UL standard 1950 recognition granted under File No. 950 certification granted under File No. [. . . ] Time from data output released-to-driving until the first transition of critical timing. First STROBE time (for device to first negate DSTROBE from STOP during a data in burst) Limited interlock time (see note 1) Interlock time with minimum (see note 1) Unlimited interlock time (see note 1) Maximum time allowed for output drivers to release (from asserted or negated) Minimum delay time required for output drivers to assert or negate (from released) Envelope time (from DMACK- to STOP and HDMARDY- during data in burst initiation and from DMACK to STOP during data out burst initiation) Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of DMARDY-) Ready-to-pause time (that recipient shall wait to pause after negating DMARDY-) Maximum time before releasing IORDY Quantum Fireball Plus AS 10. 2/20. 5/30. 0/40. 0/60. 0 GB AT 6-13 ATA Bus Interface and ATA Commands tZIORDY tACK tSS Minimum time before driving IORDY (see note 4) Setup and hold times for DMACK- (before assertion or negation) Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates a burst) Notes: 1. The parameters tUI, tMLI and tLI indicate sender-to-recipient or recipient-tosender interlocks, i. e. , one agent (either sender or recipient) is waiting for the other agent to respond with a signal before proceeding. tUI is an unlimited interlock that has no maximum time value. tMLI is a limited time-out that has a defined minimum. tLI is a limited time-out that has a defined maximum. 80-conductor cabling will be required in order to meet setup (tDS, tCS) and hold (tDH, tCH) times in modes greater than 2. Timing for tDVS, tDVH, tCVS and tCVH will be met for lumped capacitive loads of 15 and 40 pf at the connector where the Data and STROBE signals have the same capacitive load value. Due to reflections on the cable, these timing measurements are not valid in a normally functioning system. For all modes the parameter tZIORDY may be greater than tENV due to the fact that the host has a pull up on IORDY- giving it a known state when released. The parameters tDS, and tDH for mode 5 are defined for a recipient at the end of the cable only in a configuration with one device at the end of the cable. Figures 6-3 through 6-12 define the timings associated with all phases of Ultra DMA bursts. 6-14 Quantum Fireball Plus AS 10. 2/20. 5/30. 0/40. 0/60. 0 GB AT ATA Bus Interface and ATA Commands DMARQ (device) Tui DMACK(host) Tack STOP (host) Tack HDMARDY(host) Tfs Tziordy DSTROBE (device) Taz DD(15:0) Tack DA0, DA1, DA2, CS0-, CS1Tfs Tdvs Tzad Tzad Tdvh Tenv Tenv Figure 6-3 Initiating a Data In Burst T2cyc Tcyc Tdvs DSTROBE at device Tdvh DD(15:0) at device Tds Tdh Tds Tdh Tdvh Tdvh Tcyc T2cyc Tdvs Tdh DSTROBE at host DD(15:0) at host Figure 6-4 Sustained Data In Burst Note: DD(15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until well after they are driven by the device. Quantum Fireball Plus AS 10. 2/20. 5/30. 0/40. 0/60. 0 GB AT 6-15 ATA Bus Interface and ATA Commands DMARQ (device) DMACK(host) Trp STOP (host) Tsr HDMARDY (host) Trfs DSTROBE (device) DD(15:0) (device) Figure 6-5 Host Pausing a Data In Burst Note: The host knows the burst is fully paused Trp ns after HDMARDY- is negated and may then assert STOP to terminate the burst. Tsr timing need not be met for an asynchronous pause. DMARQ (device) Tdvs Tmli DMACK(host) Tli STOP (host) Tli HDMARDY(host) Tss DSTROBE (device) Taz DD(15:0) CRC Tack DA0, DA1, DA2, CS0-, CS1Tli Tiordyz Tack Tack Tzah Tdvh Figure 6-6 Device Terminating a Data In Burst 6-16 Quantum Fireball Plus AS 10. 2/20. 5/30. 0/40. 0/60. 0 GB AT ATA Bus Interface and ATA Commands Tli DMARQ (device) Tmli Tmli DMACK(host) Trp STOP (host) Tack HDMARDY(host) Trfs Tli DSTROBE (device) Tzah Taz DD(15:0) Tdvh CRC Tack DA0, DA1, DA2, CS0-, CS1Tiordyz Tack Tdvs Figure 6-7 Host Terminating a Data In Burst DMARQ (device) Tui DMACK(host) Tack STOP (host) Tziordy DDMARDY(device) Tack Tdvs HSTROBE (host) Tdvh DD(15:0) (host) Tack DA0, DA1, DA2, CS0-, CS1Tli Tui Tenv Figure 6-8 Initiating a Data Out Burst Quantum Fireball Plus AS 10. 2/20. 5/30. 0/40. 0/60. 0 GB AT 6-17 ATA Bus Interface and ATA Commands T2cyc Tcyc Tcyc T2cyc Tdvs HSTROBE at host Tdvh DD(15:0) at host Tds Tdh Tds Tdh Tdvh Tdvh Tdvs Tdh HSTROBE at device DD(15:0) at device Figure 6-9 Sustained Data Out Burst Note: DD(15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until well after they are driven by the host. Trp DMARQ (device) DMACK(host) STOP (host) Tsr DDMARDY(device) Trfs HSTROBE (host) DD(15:0) (host) Figure 6-10 Device Pausing a Data Out Burst Note: The device knows the burst is fully paused Trp ns after DDMARDY- is negated and may then negate DMARQ to terminate the burst. Tsr timing need not be met for an asynchronous pause. 6-18 Quantum Fireball Plus AS 10. 2/20. 5/30. 0/40. 0/60. 0 GB AT ATA Bus Interface and ATA Commands Tli DMARQ (device) Tmli DMACK(host) Tack Tss STOP (host) Tiordyz Tli DDMARDY(device) Tli HSTROBE (host) Tack Tdvs Tdvh DD(15:0) (host) DA0, DA1, DA2, CS0-, CS1- CRC Tack Figure 6-11 Host Terminating a Data Out Burst Quantum Fireball Plus AS 10. 2/20. 5/30. 0/40. 0/60. 0 GB AT 6-19 ATA Bus Interface and ATA Commands DMARQ (device) Trp DMACK(host) Tli STOP (host) Tiordyz DDMARDY(device) Trfs Tli HSTROBE (host) Tack Tmli Tmli Tack Tdvs Tdvh DD(15:0) (host) DA0, DA1, DA2, CS0-, CS1- CRC Tack Figure 6-12 Device Terminating a Data out Burst 6. 4. 2. 3 Host Interface RESET Timing The host interface RESET timing shown in Table 6-9 is in reference to signals at 0. 8 volts and 2. 0 volts. All times are in nanoseconds, unless otherwise noted. Table 6-9 Host Interface RESET Timing SYMBOL tM DESCRIPTION RESET­ Pulse width MINIMUM 25 MAXIMUM -- Figure 6-13 Host Interface RESET Timing 6-20 Quantum Fireball Plus AS 10. 2/20. 5/30. 0/40. 0/60. 0 GB AT ATA Bus Interface and ATA Commands 6. 5 REGISTER ADDRESS DECODING The host addresses the drive by using programmed I/O. Host address lines A0­A2, chip-select CS1FX­ and CS3FX­, and IOR­ and IOW­ address the disk registers. Host address lines A3­A9 generate the two chip-select signals, CS1FX­ and CS3FX­. · Chip Select CS1FX­ accesses the eight Command Block Registers. · Chip Select CS3FX­ is valid during 8-bit transfers to or from the Alternate Status Register. [. . . ] SEEK ­ A movement of the disk read/write head in or out to a specific track. SERVO DATA ­ Magnetic markings written on the media that guide the read/write heads to the proper position. SERVO SURFACE ­ A separate surface containing only positioning and disk timing information but no data. Quantum Fireball Plus LM 10. 2/15. 0/20. 5/30. 0 GB AT G-7 Glossary T THIN FILM ­ A type of coating, used for disk surfaces. Thin film surfaces allow more bits to be stored per disk. [. . . ]