User manual SONY CFS-W500L

[. . . ] (See *2 in the Tables 5. 9 and 5. 10) Tables 5. 11 and 5. 13 were added. Revised contents Specification No. : C141-E110-**EN The contents of this manual is subject to change without prior notice. Copyright 2000 SONY LIMITED C141-E110-03EN i This page is intentionally left blank. PREFACE This manual describes the MPG3xxxAT series, a 3. 5-inch hard disk drive with a BUILT-IN controller that is compatible with the ATA interface. This manual explains, in detail, how to incorporate the hard disk drives into user systems. [. . . ] / LBA [LSB] 00 (*1) Error information *1 If the command is terminated due to an error, this register indicates 01. C141-E110-03EN 5 - 43 (20) READ BUFFER (X'E4') The host system can read the current contents of the sector buffer of the device by issuing this command. Upon receipt of this command, the device sets the BSY bit of Status register and sets up the sector buffer for a read operation. Then the device sets the DRQ bit of Status register, clears the BSY bit, and generates an interrupt. After that, the host system can read up to 512 bytes of data from the buffer. At command issuance (I/O registers setting contents) 1F7H(CM) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 1 × 1 × 1 × 0 DV xx xx xx xx xx 0 1 xx 0 0 At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) × × × Status information DV xx xx xx xx Error information xx (21) WRITE BUFFER (X'E8') The host system can overwrite the contents of the sector buffer of the device with a desired data pattern by issuing this command. Upon receipt of this command, the device sets the BSY bit of the Status register. Then the device sets the DRQ bit of Status register and clears the BSY bit when the device is ready to receive the data. After that, 512 bytes of data is transferred from the host and the device writes the data to the sector buffer, then generates an interrupt. At command issuance (I/O registers setting contents) 1F7H(CM) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) 1 × 1 × 1 × 0 DV xx xx xx xx xx 1 0 xx 0 0 5 - 44 C141-E110-03EN At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) (22) IDLE (X'97' or X'E3') Upon receipt of this command, the device sets the BSY bit of the Status register, and enters the idle mode. Then, the device clears the BSY bit, and generates an interrupt. The device generates an interrupt even if the device has not fully entered the idle mode. If the spindle of the device is already rotating, the spin-up sequence shall not be implemented. If the contents of the Sector Count register is other than 0, the automatic power-down function is enabled and the timer starts countdown immediately. Upon receipt of this command, the device sets the BSY bit of the Status register and enters the sleep mode. The device then clears the BSY bit and generates an interrupt. The device generates an interrupt even if the device has not fully entered the sleep mode. In the sleep mode, the spindle motor is stopped and the ATA interface section is inactive. All I/O register outputs are in high-impedance state. The only way to release the device from sleep mode is to execute a software or hardware reset. At command issuance (I/O registers setting contents) 1F7H(CM) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) × × × X'99' or X'E6' DV xx xx xx xx xx xx 5 - 48 C141-E110-03EN At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) × × × Status information DV xx xx xx xx Error information xx (27) CHECK POWER MODE (X'98' or X'E5') The host checks the power mode of the device with this command. The host system can confirm the power save mode of the device by analyzing the contents of the Sector Count and Sector registers. The device sets the BSY bit and sets the following register value. After that, the device clears the BSY bit and generates an interrupt. Power save mode · During moving to standby mode · Standby mode · During returning from the standby mode · Idle mode · Active mode Sector Count register X'00' X'80' X'FF' At command issuance (I/O registers setting contents) 1F7H(CM) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(FR) × × × X'98' or X'E5' DV xx xx xx xx xx xx C141-E110-03EN 5 - 49 At command completion (I/O registers contents to be read) 1F7H(ST) 1F6H(DH) 1F5H(CH) 1F4H(CL) 1F3H(SN) 1F2H(SC) 1F1H(ER) × × × Status information DV xx xx xx X'00' or X'FF' Error information xx (28) SMART (X'B0) This command performs operations for device failure predictions according to a subcommand specified in the FR register. If the value specified in the FR register is supported, the Aborted Command error is posted. It is necessary for the host to set the keys (CL = 4Fh and CH = C2h) in the CL and CH registers prior to issuing this command. [. . . ] The write cache function is operated with the following command. · · · WRITE SECTOR(S) WRITE MULTIPLE WRITE DMA IMPORTANT When the write cache function is enabled, the transferred data from the host by the WRITE SECTOR(S) is not completely written on the disk medium at the time that the interrupt of command complete is generated. When the unrecoverable error occurs during the write operation, the command execution is stopped. Then, when the drive receives the next command, it generates an interrupt of abnormal end. [. . . ]