User manual SONY VAIO VGN-NW180J

[. . . ] 5 Nomenclature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Codes Used in Summary Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 General Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Schematic, Layout, and Routing Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] 9 Documentation Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Design Guide Update 3 Preface R Revision History Rev. -001 -002 Initial Release (1) Added Documentation Change #3, Replace Figure 118, Intel® 845 Chipset Platform Using PC133 SDRAM System Memory Power Delivery Map (2) Added Documentation Change #4, Added Section 4. 6. 7, Electrostatic Discharge Platform Recommendations (3) Added Documentation Change #5, Change Table 3, System Bus Routing Summary for the Processor (4) Added Documentation Change #6, Add Section 13. 2, Intel® Boxed Processor Mechanical Keep-Outs (5) Added Documentation Change #7, Add Section 15. 1. 3, Intel® Boxed Processor Mechanical Keep-Outs (6) Added Schematic, Layout, and Routing Updates #1, Schematic change to the 82845 MCH HSWING Circuit -003 (1) Added Documentation Change 8, Revise Section 4. 1, Schematic Checklist, Host Interface, PWRGOOD March 2004 Draft/Changes Date March 2002 May 2002 4 Design Guide Update Preface R Preface This Design Guide Update document is an update to the specifications and information contained in the Intel® Pentium® 4 Processor in 478-pin Package and Intel® 845 Chipset Platform for SDR Design Guide, January 2002. This Design Guide Update may reference other documents listed in the following Affected Documents/Related Documents table. This document is a compilation of updates to the general design considerations; schematic, layout, and routing updates; and documentation changes. This document is intended for hardware system manufacturers and for software developers of applications, operating systems, and tools. The design guide (and this design guide update) is primarily targeted at the PC market segment and was first published in 2002. Those using this design guide and update should check for device availability before designing in any of the components included in this document. Information types defined in the Nomenclature section of this document are consolidated into the public design guide update document when the public design guide document is first published. If 5V tolerance on OC:[3:0]# is needed then V5REF_SUS USB must be connected to 5V_Always/5V_AUX which remains powered during S5. 3. Replaced: Replace Figure 118, Intel® 845 Chipset Platform Using PC133 SDRAM System Memory Power Delivery Map Figure 118, Intel® 845 Chipset Platform Using PC133 SDRAM System Memory Power Delivery Map, in Section 12. 2, is replaced with the following new Power Delivery Map: Design Guide Update 11 Documentation Changes R ATX 12V Power Supply 3. 3V 5V 5VSB 12V VRM Processor Core Processor Vtt VID VREG Processor VID 1. 5 V VREG ® ® ® ® ® Intel 1. 8 V VREG Intel Intel Intel 3. 3V FET Switch Intel MCH Core 1 . 5V MCH Vtt MCH AGP MCH Hub Interface 1. 8V MCH System Memory SDR 3. 3V 3. 3V VREG PC-133 System Memory 3. 3V Intel Intel Intel 1. 8 V VREG ® ICH2 Core 1. 8V ICH2 I/O 3. 3V ICH2 Resume 1. 8V ICH2 Resume I/O 3. 3V ICH2 RTC 3. 3V ® ® ® ® Intel Intel ® Intel ICH2 V5REF Intel® ICH2 V5REF_SUS FWH 3. 3V LPC Super I/O 3. 3V CK-408 3. 3V 4. Electrostatic Discharge Platform Recommendations The following new material is added as Section 4. 6. 7, Electrostatic Discharge Platform Recommendations: 4. 6. 7 Electrostatic Discharge Platform Recommendations Electrostatic discharge (ESD) into a system can lead to system instability, and possibly cause functional failures when a system is in use. There are system level design methodologies that when followed can lead to higher ESD immunity. Electromagnetic fields due to ESD are introduced into a system through chassis openings such as the I/O back panel and PCI slots. These fields can introduce noise into signals and cause the system to malfunction. One can reduce the potential for issues at the I/O area by adding more ground plane on the motherboard around the I/O area. This can lead to a higher ESD immunity. 12 Design Guide Update Documentation Changes R Intel recommends that the I/O area on the top and bottom signal layers of a 4-layer motherboard near the I/O back panel be filled with a ground fill as shown in Figures 1-4. In addition, a ground fill cutout should be placed on the Vcc layer in the area where the ground fill is done on the top and bottom layers. Intel recommends filling the I/O area as much as possible without effecting the signal routing. The board designer should fill the entire I/O area along the board edge. [. . . ] The board designer should fill the entire I/O area along the board edge. The spacing from the ground fill to other shapes/traces should be at least 20 mils. It is recommended that these ground fill areas be connected to two chassis mounting holes (as seen in Figure 2). This will allow ESD current to travel to the chassis instead of the board. [. . . ]