User manual TEKTRONIX BERTSCOPE BSA DATASHEET

[. . . ] Bit Error Rate Tester BERTScope® BSA Series Data Sheet Jitter Tolerance Compliance Template Testing with Margin Testing Physical Layer Test Suite with Mask Testing, Jitter Peak, BER Contour, and Q-factor Analysis for Comprehensive Testing with Standard or User-defined Libraries of Jitter Tolerance Templates Integrated Eye Diagram Analysis with BER Correlation Optional Jitter Map Comprehensive Jitter Decomposition ­ with Long Pattern (i. e. PRBS-31) Jitter Triangulation to Extend BER-based Jitter Decomposition Beyond the Limitations of Dual Dirac TJ, DJ, and RJ for a Comprehensive Breakdown of Jitter Subcomponents Patented Error Location AnalysisTM enables Rapid Understanding of your BER Performance Limitations and Assess Deterministic versus Random Errors, Perform Detailed Pattern-dependent Error Analysis, Perform Error Burst Analysis, or Error-free Interval Analysis Features & Benefits Pattern Generation and Error Analysis, High-speed BER Measurements up to 26 Gb/s Integrated, Calibrated Stress Generation to Address the Stressed Receiver Sensitivity and Clock Recovery Jitter Tolerance Test Requirements for a Wide Range of Standards Sinusoidal Jitter to 100 MHz Random Jitter Bounded, Uncorrelated Jitter Sinusoidal Interference Spread Spectrum Clocking PCIe 2. 0 Receiver Testing F/2 Jitter Generation for 8xFC and 10GBASE-KR Testing Electrical Stressed Eye Testing for: PCI Express 10/40/100 Gb Ethernet SFP+/SFI XFP/XFI OIF/CEI Fibre Channel SATA USB 3. 0 Applications Design Verification including Signal Integrity, Jitter, and Timing Analysis Design Characterization for High-speed, Sophisticated Designs Certification Testing of Serial Data Streams for Industry Standards Design/Verification of High-speed I/O Components and Systems Signal Integrity Analysis ­ Mask Testing, Jitter Peak, BER Contour, Jitter Map, and Q-factor Analysis Design/Verification of Optical Transceivers Data Sheet Linking Domains Eye diagrams have always provided an easy and intuitive view of digital performance. It has been harder to tie this directly with BER performance, as the instruments that provide views of each have been architected in fundamentally different ways. Eye diagrams have been composed of shallow amounts of data that have not easily uncovered rarer events. [. . . ] Frequency Range 0. 125 to 3. 125 GHz (12. 5 GHz with Option STR) Amplitude Range 1 Vp-p, nominal, centered around 0 V Transition Time <500 ps Interface SMA female, 50 , DC coupled into 0 V Trigger Output Characteristic Description Provides a pulse trigger to external test equipment. Divided Clock Mode: Pulses at 1/256th of the clock rate 2. Pattern Mode: Pulse at a programmable position in the pattern (PRBS), or fixed location (RAM patterns) Stress modulation added on models so equipped, when enabled. Minimum Pulse Width 128 Clock Periods (Mode 1) 512 Clock Periods (Mode 2) Transition Time <500 ps Jitter (p-p, data to trigger) <10 ps, typical (BSA175C/CPG, BSA260C/CPG) >300 mVp-p, center at 650 mV Output Levels Interface 50 SMA female Allows use of external low-frequency jitter source to modulate the stressed pattern generator output. Frequency Range DC to 100 MHz Jitter Amplitude Range Up to 1. 1 ns, can be combined with other internal low-frequency modulation Input Voltage Range 0-2 Vp-p (+10 dBm) for normal operation 6. 3 Vp-p (+20 dBm) max nondestructive input Data Rate Range Up to 8. 5 Gb/s (BSA85C/CPG), 12. 5 Gb/s (BSA125C/CPG), 17. 5 Gb/s (BSA175C/CPG), and 22 Gb/s (BSA260C/CPG) Interface SMA female 50 , DC coupled into 0 V Low-frequency Sinusoidal Jitter Output (Option STR Only) Characteristic Description To allow phasing of two BERTScopes together, in-phase or anti-phase. Frequency As set for internal SJ from GUI Amplitude 2 Vp-p, centered at 0 V Interface SMA female 10 www. tektronix. com Bit Error Rate Tester -- BERTScope® BSA Series Reference Input Characteristic Description To lock the BERTScope to an external frequency reference from of another piece of equipment. Frequency 10, 100, 106. 25, 133. 33, 156. 25, 166. 67, or 200 MHz Amplitude 0. 325 to 1. 25 Vp-p (­6 to +6 dBm) Interface 50 SMA female, AC coupled Reference Output Characteristic Description Available divide ratios from clock-related output, by bit rate, using the internal clock, BSA85C***. Provides a frequency reference for other instruments to lock to. Configuration Single Ended (Ref-Out not used) (BSA125C, CPG) Differential Frequency 10, 100, 106. 25, 133. 33, 156. 25, 166. 67, or 200 MHz Amplitude 1 Vp-p (+4 dBm) nominal, each output, (2 Vp-p differential) Interface 50 SMA female, AC coupled BSA125C, CPG, BSA175C, CPG, and BSA260C, CPG Clock Path Details BSA85C, CPG Functional block diagram of the clock path for models with stress capability, BSA85C/CPG, BSA125C/CPG, BSA175C/CPG, BSA260C/CPG. * This output can also provide a full-rate jittered clock. ** Stress may be added to an external clock on appropriate models. Stress operating range is from 1. 5 to 11. 2 Gb/s. External clock must have a duty cycle of 50% ±2%. *** All listed ratios available for an external clock input over entire bit rate range, limitations for internal clock only. Minimum specified frequency of the clock output is 100 MHz. Operation below this rate will be uncalibrated. Functional block diagram of the clock path for models with stress capability, BSA85C/CPG. The BSA125, BSA175, and BSA260 models use an internal Double Data Rate (DDR) architecture to operate at data rates 11. 2 Gb/s. When operating at 11. 2 Gb/s or higher data rate, the clock output will be 1/2 the data rate. External clock can be specified to be either full or half data rate. When full rate is selected, the pattern generator will operate in DDR mode when the input clock frequency is 11. 2 GHz or higher. These ratios apply to operation from internal clock only. External clock will be output at 1/2 rate when half rate is selected, or when full rate is selected and clock rate is 11. 2 GHz. The minimum data rate specified for the main clock output is 500 Mb/s. Output will be uncalibrated when operated at divided rates lower than 500 Mb/s. www. tektronix. com 11 Data Sheet Available Multi-rate and Sub-rate Divider Ratios for Main Clock Output, BSA125C, CPG, BSA175C, CPG, and BSA260C, CPG Models Data Rate (Gb/s) Ratios for Main Clock Out Ratios for Sub-rate Clock Out*3 Pattern Generator Stressed Eye Flexible, integrated stressed eye impairment addition to the internal or an external clock Easy setup, with complexity hidden from the user with no loss of flexibility Verify compliance to multiple standards using the BERTScope and external ISI filters. Standards such as: OIF CEI 6 Gb SATA PCI Express® XFI USB 3. 0 SONET SAS 2 XAUI 10 and 100 Gb Ethernet DisplayPort Sinusoidal interference may be inserted in-phase or in anti-phase, or sent externally to be summed after an external ISI reference channel Sinusoidal jitter may be locked between two BERTScopes in-phase or anti-phase, as required by OIF CEI Flexible External Jitter Interfaces 500-750 Mb/s 0. 75-1. 5 Gb/s 1. 5-3 Gb/s 3-6 Gb/s 6-11. 2 Gb/s 11. 2-12 Gb/s 12-26 Gb/s 1, 2, 4, 5, 6, 7, 8, 9, 10, 12, 14, 16, 18, 20, 24, 32, 36 1, 2, 4, 5, 6, 7, 8, 9, 10, 12, 14, 16, 18, 20, 24, 25, 28, 30, 32, 35, 36, 40, 42, 45, 48, 54, 56, 64, 72, 81 1, 2, 4, 5, 6, 7, 8, 9, 10, 12, 14, 16, 18, 20, 24, 30, 32, 32, 35, 36, 36, 40, 42, 45, 48, 50, 54, 56, 60, 64, 70, 72, 80, 81, 84, 90, 98, 108, 112, 126, 128, 144, 162 1, 2, 4, 5, 6, 7, 8, 9, 10, 12, 14, 16, 18, 20, 24, 30, 32, 32, 35, 36, 36, 40, 42, 45, 48, 50, 54, 56, 60, 64, 70, 72, 80, 81, 84, 90, 98, 100, 108, 112, 120, 126, 128, 140, 144, 160, 162, 168, 180, 192, 196, 216, 224, 252, 256, 288, 324 1, 2, 4, 5, 6, 7, 8, 9, 10, 12, 14, 16, 18, 20, 24, 30, 32, 32, 35, 36, 36, 40, 42, 45, 48, 50, 54, 56, 60, 64, 70, 72, 80, 81, 84, 90, 98, 108, 112, 126, 128, 140, 144, 144, 160, 162, 162, 168, 180, 192, 196, 200, 216, 224, 240, 252, 256, 280, 288, 320, 324, 360, 384, 392, 432, 448, 504, 512, 576, 648 2, 4, 8, 10, 12, 14, 16, 18, 20, 24, 28, 32, 36, 40, 48, 60, 64, 64, 70, 72, 72, 80, 84, 90, 96, 100, 108, 112, 120, 128, 140, 144, 160, 162, 168, 180, 196, 200, 216, 224, 240, 252, 256, 280, 288, 320, 324, 336, 360, 384, 392, 432, 448, 504, 512, 576, 648 2, 4, 8, 10, 12, 14, 16, 18, 20, 24, 28, 32, 36, 40, 48, 60, 64, 64, 70, 72, 72, 80, 84, 90, 96, 100, 108, 112, 120, 128, 140, 144, 160, 162, 168, 180, 196, 216, 224, 252, 256, 280, 288, 288, 320, 324, 324, 336, 360, 384, 392, 400, 432, 448, 480, 504, 512, 560, 576, 640, 648, 720, 768, 784, 864, 896, 1008, 1024, 1152, 1296 1, 2, 4 1, 2, 4, 8 1, 2, 4, 8, 16 1, 2, 4, 8, 16, 32 1, 2, 4, 8, 16, 32, 64 Front Panel External High Frequency Jitter Input Connector ­ Jitter from DC to 1. 0 GHz up to 0. 5 UI (max) may be added, of any type that keeps within amplitude and frequency boundaries Rear Panel External SJ Low Frequency Jitter Input Connector ­ Jitter from DC to 100 MHz up to 1 ns (max) may be added 2, 4, 8, 16, 32, 64 Rear Panel SJ Output Sinusoidal Interference Output Rear Panel Connector Note: Internal RJ, BUJ, and external high-frequency jitter input limited to 0. 5 UI, combined, further limited to 0. 25 UI each when both are enabled. [. . . ] Many views come standard with the BERTScope Family. Characteristic Description Live Analysis Error Logging Capacity Error Events/Second Maximum Burst Length Continuous Max. 2 GB file size 10, 000 32 kb 18 www. tektronix. com Bit Error Rate Tester -- BERTScope® BSA Series Error Analysis Options Forward Error Correction Emulation Because of the patented error location ability of the BERTScope, it knows exactly where each error occurs during a test. By emulating the memory blocks typical of block error correcting codes such as Reed-Solomon architectures, bit error rate data from uncorrected data channels can be passed through hypothetical error correctors to find out what a proposed FEC approach would yield. Users can set up error correction strengths, interleave depths, and erasure capabilities to match popular hardware correction architectures. [. . . ]