User manual TEKTRONIX DDR MEMORY BUS ELECTRICAL VALIDATION AND ANALYSIS SOFTWARE DATASHEET

[. . . ] The user selects which DDR technology, speed grade, and measurement group (reads, writes, clocks, address, and control lines) they are testing, using check boxes to select some or all measurements in a category. DDRA can then automate oscilloscope scale selection, DQ and DQS level selections, and threshold detection, then automate burst identification using search and mark. Search and mark (for read/write measurements) data is used to identify and separate all read vs. [. . . ] In addition to the measurements shown below (for DDR2 in this example), Option DDRA also performs de-rating of Setup and Hold pass/fail limits based on the result of slew rate measurements, as stipulated by JEDEC in the test specs for DDR2 and DDR3 (JESD79-3D, JESD79-2E as of this writing). JEDEC Measurements Supported for DDR2 tCK (avg) tCK (abs) tCH (avg) tCH (abs) tCL (avg) tCL (abs) tHP tJIT (duty) tJIT (per) tJIT (cc) tERR (02) tERR (03) tERR (04) tERR (05) tERR (6 - 10 per) tERR (11 - 50 per) tDQSH tDQSL tDS - diff (base) tDS - SE (base) tDS - diff - DERATED tDS - SE - DERATED tDH - diff (base) tDH - SE (base) tDH - diff - DERATED tDH - SE - DERATED tDIPW tAC - diff tDQSCK - diff tDQSCK - SE tDQSQ - diff tDQSQ - SE tQH tDQSS tDSS tDSH tIPW tIS (base) tIH (base) tIS - DERATED tIH - DERATED Vid - diff (AC) Vix (AC) - DQS Vix (AC) - CLK Vox (AC) - DQS Vox (AC) - CLK InputSlew - Rise (DQS) InputSlew - Fall (DQS) InputSlew - Rise (CLK) InputSlew - Fall (CLK) AC - Overshoot Amplitude - diff AC - Undershoot Amplitude - diff AC - Overshoot Amplitude - SE AC - Undershoot Amplitude - SE Data Eye Width Additional Capabilities using a Performance MSO (Mixed-Signal Oscilloscope) The MSO70000 Series Performance MSOs allow you to probe more signals on the DDR bus and to trigger on and view specific bus events. Up to 16 digital channels can be used to view logic states of command and address signals such as RAS, CAS, WE, CE, CS, etc. Signal integrity of these 16 inputs can be analyzed using the iCaptureTM multiplexing feature, which allows any of the digital input signals to be internally routed to one of the scope's four analog channels. Events such as initialization, power state changes, and command-bus cycle timing can also be analyzed using the bus-decoding features of the MSO. Full Bus Analysis using Logic Analyzer and Oscilloscope When full protocol analysis or probing of the entire memory bus is required, a logic analyzer can provide this additional capability. The TLA7000 Series logic analyzers can also be linked with Tektronix oscilloscopes to provide an integrated test setup using tools such as iCapture mentioned above. This eliminates the need for double probing and allows full analog capture of any signals probed by the logic analyzer. In addition, the iViewTM display interface allows transfer of the oscilloscope data to the logic analyzer display, so that data from both instruments are analyzed and time-aligned on one display screen. 2 www. tektronix. com DDR Memory Bus Electrical Validation and Analysis Software Characteristics Bandwidth Recommendations for Each DDR Standard DDR Type Maximum Data Rate Clock Rate 5th Harmonic of Clock Max SE Slew Rate (JEDEC) Typical Signal Swing Oscilloscope Rise Time 10% - 90%*1 Recommended Oscilloscope BW*2 DDR DDR2 DDR3 400 MT/s 800 MT/s 1600 MT/s 200 MHz 400 MHz 800 MHz 1 GHz 2 GHz 4 GHz 5 V/ns 5 V/ns 5 V/ns 1. 8 V 1. 25 V 1. 0 V 89 ps 62 ps 49 ps 4 GHz 6 GHz 8 GHz *1 For 3% maximum error on rise-time measurement. *2 For less stringent applications, a one-step reduction in scope bandwidth may be acceptable. Ordering Information DDRA DDR Memory Bus Electrical Validation and Analysis Oscilloscope Software. To order a floating license for an existing DPO7000, DPO70000B, DSA70000B, or MSO70000 use the orders listed below: Order Description To order on a new DPO7000, DPO70000B, DSA70000B*3, or MSO70000: Order Description DPOFL-DDRA DPOFL-ASM DPOFL-DJA DDR Memory Technology Analysis Package ­ Floating License Advanced Event Search and Mark ­ Floating License DPOJET Jitter and Eye Diagram Analysis ­ Floating License Opt. DDRA DPOFL-DDRA Preinstall on a new DPO7000, DPO70000, DSA70000, or MSO70000 Series oscilloscope*4 DDR Memory Technology Analysis Package ­ Floating License Recommended Accessories Order Description *3 Note: Opt. DJA and ASM are standard on the DSA70000B Series oscilloscopes. ASM (Advanced Event Search and Mark) and Opt. DJA (DPOJET) are required. To upgrade an existing DPO7000, DPO70000, DSA70000, or MSO70000 order the appropriate model number and option listed below. For example, DPO7UP DDRA. DPO7000 DPO70000B DSA70000B MSO70000 P7500 Series 020-2955-xx 020-3022-xx 020-2954-xx P6780 TriModeTM Differential Probe Micro-coax Tips (TriMode) for P7500 probes Micro-coax Tips (TriMode) for P7500 probes*5 Socket Cable for P7500 probes Differential Logic Probe for MSO70000 Recommended Nexus Technology Accessories DPO7UP DDRA ASM DJAM DJAH DJAU DJUP DPO7UP DPO7UP DPO-UP Upgrade options for DPO7000, DPO70000B, DSA70000B, MSO70000 Upgrade to option DDRA (requires options ASM and DJA) Upgrade DPO70000B and MSO70000 with Advanced Event Search and Mark (Opt. ASM) Upgrade DPO7000 with DPOJET Jitter and Eye Diagram Analysis (Opt. DJA) Upgrade DPO70404B - DPO70804B or MSO70404 MSO70804 with DPOJET Jitter and Eye Diagram Analysis (Opt. DJA) Upgrade DPO71254B - DPO72004B or MSO71254 MSO72004 with DPOJET Jitter and Eye Diagram Analysis (Opt. [. . . ] Information in this publication supersedes that in all previously published material. Specification and price change privileges reserved. TEKTRONIX and TEK are registered trademarks of Tektronix, Inc. [. . . ]