User manual TEKTRONIX TLA7000 DATASHEET

[. . . ] Tektronix Logic Analyzers TLA7000 Series Data Sheet PCI Express Gen1 through Gen3 including Gen3 Protocol to Physical Layer Analysis for Link Widths from x1 through x16 with up to 8. 0 GT/s Acquisition Rates and up to 16 GB Deep Memory (for x16 Link) Comprehensive PCI Express Probing Solutions, including Midbus, Slot Interposer, and Solder-down Connectors Modular Mainframes provide Flexibility and Expandability Supports up to 6, 528 Logic Analyzer Channels, 48 Independent Buses Broad Processor and Bus Support Applications FPGA Debug and Verification MIPI Protocol Analysis DDR2 and DDR3 Debug and Verification Signal Integrity Features & Benefits 68/102/136 Channel Logic Analyzers with up to 512 Mb Record Length MagniVuTM Acquisition Technology provides up to 20 ps (50 GHz) Timing Resolution to Find and Measure Elusive Timing Problems Quickly Up to 156 ps (6. 4 GHz)/512 Mb Record Length Timing Analysis Up to 1. 4 GHz Clock with up to 3. 0 Gb/s Data with a Data Valid Window of 180 ps for State Acquisition Analysis of High-performance Synchronous Buses Glitch and Setup/Hold Triggering and Display Finds and Displays Elusive Hardware Problems Transitional Storage Extends the Signal Analysis Capture Time for Signals that Transition Infrequently Simultaneous State, High-speed Timing, and Analog Analysis through the Same Probe Pinpoints Elusive Faults Compression Probing System with 0. 5 pF Capacitive Loading Eliminates Need for Onboard Connectors, Minimizes Intrusion on Circuits, and is Ideal for Differential Signal Applications Trace Problems from Symptom back to Root Cause in Real Time across Multiple Modules by Viewing Time-correlated Data in a Wide Variety of Display Formats PCI Express Debug from Protocol Layer to Physical Layer Silicon Validation Computer System Validation Embedded System Debug and Validation Processor/Bus Debug and Verification Embedded Software Integration, Debug, and Verification Breakthrough Solutions for Real-time Digital Systems Analysis Tektronix provides breakthrough digital systems analysis tools that enable digital hardware and software designers to capture and analyze the source of elusive problems that threaten product development schedules. The TLA7000 Series provides the speed you need to capture the source of those elusive problems, plus the visibility you want with large displays and fast system data throughput, while protecting your investment with compatibility with all TLA modules. Data Sheet TLA7012 and TLA7016 Mainframes The TLA7012 Portable and TLA7016 Benchtop mainframes are modular mainframes that accept TLA logic analyzer and pattern generator modules. The TLA7012 and TLA7016 can be configured as either master or expansion mainframes to provide solutions for large numbers of buses and high channel-count requirements. The TLA7012 Portable Mainframe and TLA7016 Benchtop Mainframe along with the TLAPC1 Benchtop Controller are built on a Microsoft Windows XP Professional PC platform that offers a familiar work environment for the TLA application software. [. . . ] Basic Analog Multiplexer functionality is offered standard on all TLA7ACx modules. This routes 4 fixed channels to the iCapture Analog Output BNCs. The outputs cannot be switched to other logic analyzer channels. Option AM enables full analog multiplexer control and allows the routing of any 4 logic analyzer channels to the iCapture Analog Output BNCs 6 www. tektronix. com Tektronix Logic Analyzers -- TLA7000 Series Trigger Characteristics Characteristic Description Physical Characteristics Dimensions mm in. Independent Trigger States Maximum Independent If/Then Clauses per State Maximum Number of Events per If/Then Clause Maximum Number of Actions per If/Then Clause Maximum Number of Trigger Events Number of Word Recognizers Number of Transition Recognizers Number of Range Recognizers Number of Counters/Timers Trigger Event Types 16 16 Height Width Depth Weight 262 61 381 kg 10. 3 2. 4 15 lb. 8 Net Shipping 3. 1 6. 3 6. 7 13. 7 8 TLA7Bxx Characteristics General Characteristic Description 18 (2 counters/timers plus any 16 other resources) 16 16 4 2 Word, Group, Channel, Transition, Range, Anything, Counter Value, Timer Value, Signal, Glitch, Setup-and-Hold Violation, Snapshot Trigger Module, Trigger All Modules, Trigger Main, Trigger MagniVu, Store, Don't Store, Store Sample, Increment Counter, Decrement Counter, Reset Counter, Start Timer, Stop Timer, Reset Timer, Snapshot Current Sample, Goto State, Set/Clear Signal, Do Nothing 1250 Mb/s (4X clocking mode) DC to 500 MHz (2 ns) 51 bits each (>50 days at 2 ns) DC to 500 MHz (2 ns) 500 MHz (2 ns) 2 ns Double bounded (408 channel max). Can be as wide as any group, must be grouped according to specified order of significance From 8 ns before to 7 ns after clock edge in 125 ps increments. This range may be shifted towards the positive region by 0 ns, 4 ns, or 8 ns From 7 ns before to 8 ns after clock edge in 125 ps increments. This range may be shifted towards the positive region by 0 ns [+8, ­8] ns, 4 ns [+12, ­4] ns, or 8 ns [+16, 0] ns Any data sample MagniVu position can be set from 0% to 60% centered around the MagniVu trigger Global (conditional), by state (start/stop), block, by trigger action, or transitional. Also force main prefill selection available Trigger Action Types Maximum Triggerable Data Rate Trigger Sequence Rate Counter/Timer Range Counter Rate Timer Clock Rate Counter/Timer Latency Range Recognizers Number of Channels (All channels are acquired including clocks) TLA7BB2 68 channels (4 are clock channels) TLA7BB3 102 channels (4 are clock, 2 are qualifier channels) TLA7BB4 136 channels (4 are clock, 4 are qualifier channels) TLA7BC4 136 channels (4 are clock, 4 are qualifier channels) (128 Mb) Channel grouping No limit to number of groups or number of channels per group (all channels can be reused in multiple groups) Module "Merging" Up to five 68-channel, 102-channel, or 136-channel modules can be "merged" to make up to a 680-channel module. Merged modules exhibit the same depth as the lesser of the five individual modules. Word/setup-and-hold/glitch/transition recognizers span all five modules. Range recognizers limited to three module merge. Only one set of clock connections is required. Time Stamp 54 bits at 20 ps resolution (>4 days duration) Clocking/Acquisition Modes Asynchronous and Synchronous. 20 ps (50 GHz) MagniVu, high-speed timing is available simultaneous with all modes 1 Number of Mainframe Instrument Slots Required per TLA Series Module Input Characteristics (with P6800 or P6900 Series probes) Characteristic Description Capacitive Loading Setup-and-Hold Violation Recognizer Setup Time Range Setup-and-Hold Violation Recognizer Hold Time Range Trigger Position MagniVu Trigger Position Storage Control (Data qualification) 0. 5 pF clock/data (P6900 Series) <0. 7 pF clock/data (P6800 Series); 1. 0 pF for P6810 when 8-channel podlet grouper is used Threshold Selection Range From ­2. 0 V to +4. 5 V in 5 mV increments Threshold presets include TTL (1. 5 V), CMOS (2. 5 V), ECL (­1. 3 V), PECL (3. 7 V), LVPECL (2. 0 V), LVCMOS 1. 5 V (0. 75 V), LVCMOS 1. 8 V (0. 9 V), LVCMOS 2. 5 V (1. 25 V), LVCMOS 3. 3 V (1. 65 V), LVDS (0 V), and user defined Threshold Selection Separate selection for each of the clock/qualifier and Channel Granularity individual channels Threshold Accuracy ±(35 mV + 1%) (including probe) Input Voltage Range ­2. 5 V to 5. 0 V Operating Nondestructive ±15 V Minimum Input Signal 200 mV (single ended) Swing V MAX ­ V MIN > 100 mV (differential) Input Signal Minimum Slew 200 mV/ns typical Rate www. tektronix. com 7 Data Sheet State Acquisition Characteristics (with P6800 or P6900 Series probes) Configuration Full Channel Half Channel 750 MHz Standard 1. 4 GHz Optional 750 MHz / 750 Mb/s (1 sample/clock) 750 MHz / 1. 5 Gb/s (2 samples/clock) 1. 4 GHz / 1. 4 Gb/s (1 sample/clock) Description 750 MHz / 3 Gb/s (4 samples/clock) 1. 4 GHz / 2. 8 Gb/s (2 samples/clock) Characteristic State Record Length with Time Stamps (Half/Full channels) Setup-and-Hold Time Selection Range Setup-and-Hold Window, Single Channel Minimum Clock Pulse Width 200 ps (P6960, P6964, P6980, P6982, P6860, P6864, P6880), 250 ps (P6810) Demux Channel Selection Channels can be demultiplexed to other channels through user interface with 8-channel granularity 4/2 Mb, 8/4 Mb, 16/8 Mb, 32/16 Mb, 64/32 Mb, 128/64 Mb per channel, 256/128 Mb per channel (TLA7BC4) From 15 ns before, to 7. 5 ns after clock edge in 20 ps increments. Range may be shifted towards the setup region by 0 ns [+7. 5, ­7. 5] ns, 2. 5 ns [+10, ­5] ns, or 7. 5 ns [+15, 0] ns 180 ps typical AutoDeskew and Customer Deskew Fixture Tektronix recommends AutoDeskew, a standard feature available within the TLA Application, for deskewing probe channels and setting the sample point for synchronous applications. However, for tight time alignment in both synchronous and asynchronous applications (including MagniVu), Tektronix recommends the Customer Deskew Fixture. This is an optional accessory to the TLA7Bxx modules that is used to perform a "channel-to-channel deskew" of the probes connected to the TLA7Bxx module to ensure tight time alignment between all channels across all probes. Two different fixtures are available: Timing Acquisition Characteristics (with P6800 or P6900 Series probes) Characteristic Description Customer Deskew Fixture for P6800 Series Probes Customer Deskew Fixture for P6900 Series Probes For ordering details, please see the Ordering Information section. MagniVuTM Timing MagniVu Timing Record Length Deep Timing Resolution (Quarter/Half/Full channels) Deep Timing Resolution with Glitch Storage Enabled Deep Timing Record Length (Quarter/Half/Full channels) 20 ps max, adjustments to 40 ps, 80 ps, 160 ps, 320 ps, and 640 ps 128 Kb per channel, with adjustable trigger position 156. 25 ps / 312. 5 ps / 625 ps to 50 ms 1. 25 ns to 50 ms Analog Acquisition Characteristics (with P6800 or P6900 Series probes) Characteristic Description 8/4/2 Mb, 16/8/4 Mb, 32/16/8 Mb, 64/32/16 Mb, 128/64/32 Mb, 256/128/64 Mb per channel; 512/256/128 (TLA7BC4) Deep Timing Record Length Half of default main memory depth with Glitch Storage Enabled Channel-to-Channel Skew (module + probes) Before customer deskew ±80 ps typical After customer deskew ±20 ps typical (see AutoDeskew information below) Minimum Recognizable 200 ps (P6960, P6964, P6980, P6982, P6860, Pulse/Glitch Width P6864, P6880) (Single channel) 250 ps (P6810) Minimum Detectable 40 ps Setup/Hold Violation Minimum Recognizable Sample period + channel-to-channel skew Multichannel Trigger Event Bandwidth Attenuation Offset and Gain (Accuracy) Channels Demultiplexed Run/Stop Requirements iViewTM Analog Outputs iView Analog Output BNC Cables 3 GHz (typical) 10X, ±1% ±50 mV, ±2% of signal amplitude 4 None, analog outputs are always active Compatible with any supported external Tektronix oscilloscope Four (4) low loss, 10X, 36 in. Physical Characteristics Dimensions mm in. Height Width Depth Weight 262 61 381 kg 10. 3 2. 4 15 lb. Net Shipping 3. 1 6. 3 6. 7 13. 7 8 www. tektronix. com Tektronix Logic Analyzers -- TLA7000 Series Trigger Characteristics Characteristic Description TLA7SAxx Characteristics General Characteristic Description Independent Trigger States Maximum Independent If/Then Clauses per State Maximum Number of Events per If/Then Clause Maximum Number of Actions per If/Then Clause Maximum Number of Trigger Events Number of Word Recognizers Number of Transition Recognizers Number of Range Recognizers Number of Counters/Timers Trigger Event Types 16 16 8 8 26 (2 counters/timers plus any 24 other resources) 24 24 8 Number of Lanes TLA7SA08 TLA7SA16 Record Length 2 Word, Group, Channel, Transition, Range, Anything, Counter Value, Timer Value, Signal, Glitch, Setup-and-Hold Violation, Snapshot Trigger Action Types Trigger Module, Trigger All Modules, Trigger Main, Trigger MagniVu, Store, Don't Store, Start Store, Stop Store, Increment Counter, Decrement Counter, Reset Counter, Start Timer, Stop Timer, Reset Timer, Snapshot Current Sample, Goto State, Set/Clear Signal, Do Nothing Maximum Triggerable Data 3. 0 Gb/s Rate Trigger Sequence Rate DC to 800 MHz (1. 25 ns) Counter/Timer Range 48 bits each (~4 days at 1. 25 ns) Counter Rate DC to 800 MHz (1. 25 ns) Timer Clock Rate 800 MHz (1. 25 ns) Counter/Timer Test Latency 0 ns Range Recognizers Double bounded (408 channel max). Can be as wide as any group, must be grouped according to specified order of significance Setup-and-Hold Violation Recognizer From 7. 5 ns before to 7. 5 ns after clock edge in 20 ps Setup time range increments. This range may be shifted towards the Hold time range positive region by 0 ns, 2. 5 ns, 5 ns, or 7. 5 ns Trigger Position Any data sample MagniVu Trigger Position MagniVu position can be set from 0% to 60% centered around the MagniVu trigger Storage Control All, Global (conditional), by state (start/stop), block, (Data qualification) by trigger action, or transitional. Also force main prefill selection available 8 lanes 16 lanes 8 GB x8 / 16 GB x16 with 160 MS per lane (160 ms at 8 Gb; 320 ms at 5 Gb; 640 ms at 2. 5 Gb at 100% bus utilization) 62 hours Time Stamp Range 54 bits at 25 ps resolution Time Stamp Clocking/Acquisition Modes TLA module without SSC (Spread Spectrum Clocking) , External Reference Clock (100 Mhz ±10% or 125 Mhz) with or without SSC External reference clock ±300 ppm frequency tolerance 1 Number of Mainframe Instrument Slots Required per TLA Series Module Module Configuration Requirements Module X1 Bi-Directional Link Width X4 X8 X16 TLA7SA08 TLA7SA16 1 1 1 1 0 1 0 2 Input Characteristics (with P6700 Series probes) Characteristic Description Capacitive Loading Minimum Data Eye See P6700 Series Probe Manual See P6700 Series Probe Manual Acquisition Characteristics (with P6700 Series probes) Characteristic Description Dynamic Link-width Switch Latency FTS Support Consumes up to 48 symbols (typical) PCIe Gen1&2: Consumes up to <12 FTS packets (typical) PCIe Gen3: Consumes <4 FTS packets (typical) Filter Characteristics Characteristic Description Ordered Sets DLLPs TLPs TS1, TS2, SKP, EIOS, FTS, EIEOS Ack, Nak, PM, Vendor Specific, InitFC1, InitiFC2, UpdateFC MRd, MRdL, MWr, IORd, IOWr, CfgRd0, CfgWr0, CfgRd1, CfgWr1, Msg, MsgD, Cpl, CplD, CPlLk, CPlDLk www. tektronix. com 9 Data Sheet Trigger Characteristics Characteristic Description Ordering Information Portable Logic Analyzer Mainframe, holds two TLA modules. Includes: Mini Keyboard (119-7275-xx), Optical Wheel Mouse (119-7054-xx), Front-panel cover (200-4939-xx), One dual-wide panel filler for empty slots (333-4206-xx), TLA Application Software CD (063-3881-xx), Certificate of Traceable Calibration. [. . . ] CA1 provides a single calibration event or coverage for the designated calibration interval, whichever comes first Opt. D3 Calibration Data Report, 3 Years (with Opt. D5 Calibration Data Report, 5 Years (with Opt. G3 Complete Care 3 Years (includes loaner, scheduled calibration and more). [. . . ]