User manual TEXAS INSTRUMENTS AM1705 ARM MICROPROCESSOR FEATURES 10-2010

[. . . ] AM1705 www. ti. com SPRS657B ­ FEBRUARY 2010 ­ REVISED OCTOBER 2010 AM1705 ARM Microprocessor Check for Samples: AM1705 1 AM1705 ARM Microprocessor 1. 1 123 Features ­ 32 Independent DMA Channels ­ 8 Quick DMA Channels ­ Programmable Transfer Burst Size 128K-Byte RAM Memory 3. 3V LVCMOS IOs (except for USB interface) Two External Memory Interfaces: ­ EMIFA · NOR (8-Bit-Wide Data) ­ EMIFB · 16-Bit SDRAM With 256MB Address Space Three Configurable 16550 type UART Modules: ­ UART0 With Modem Control Signals ­ 16-byte FIFO ­ 16x or 13x Oversampling Option ­ Autoflow control signals (CTS, RTS) on UART0 only Two Serial Peripheral Interfaces (SPI) Each With One Chip-Select Programmable Real-Time Unit Subsystem (PRUSS) ­ Two Independent Programmable Realtime Unit (PRU) Cores · 32-Bit Load/Store RISC architecture · 4K Byte instruction RAM per core · 512 Bytes data RAM per core · PRU Subsystem (PRUSS) can be disabled via software to save power ­ Standard power management mechanism · Clock gating · Entire subsystem under a single PSC clock gating domain ­ Dedicated interrupt controller ­ Dedicated switched central resource Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) Two Master/Slave Inter-Integrated Circuit (I2C BusTM) USB 2. 0 OTG Port With Integrated PHY (USB0) ­ USB 2. 0 Full-Speed Client ­ USB 2. 0 Full-/Low-Speed Host · Highlights ­ 375/456-MHz ARM926EJ-STM RISC Core ­ ARM9 Memory Architecture ­ Programmable Real-Time Unit Subsystem ­ Enhanced Direct-Memory-Access Controller 3 (EDMA3) ­ Two External Memory Interfaces ­ Three Configurable 16550 type UART Modules ­ Two Serial Peripheral Interfaces (SPI) ­ Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) ­ Two Master/Slave Inter-Integrated Circuit ­ USB 2. 0 OTG Port With Integrated PHY ­ Two Multichannel Audio Serial Ports ­ 10/100 Mb/s Ethernet MAC (EMAC) ­ One 64-Bit General-Purpose Timer ­ One 64-bit General-Purpose/Watchdog Timer ­ Three Enhanced Pulse Width Modulators ­ Three 32-Bit Enhanced Capture Modules · Applications ­ Industrial Automation ­ Home Automation ­ Test and Measurement ­ Portable Data Terminals ­ Educational Consoles ­ Power Protection Systems · 375/456-MHz ARM926EJ-STM RISC Core ­ 32-Bit and 16-Bit (Thumb®) Instructions ­ Single Cycle MAC ­ ARM® Jazelle® Technology ­ EmbeddedICE-RTTM for Real-Time Debug · ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 16K-Byte Data Cache ­ 8K-Byte RAM (Vector Table) ­ 64K-Byte ROM · Enhanced Direct-Memory-Access Controller 3 (EDMA3): ­ 2 Transfer Controllers 1 · · · · · · · · · 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ARM926EJ-S, EmbeddedICE-RT, ETM9, CoreSight are trademarks of ARM Limited. ARM, Jazelle are registered trademarks of ARM Limited. Copyright © 2010, Texas Instruments Incorporated ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. ADVANCE INFORMATION AM1705 SPRS657B ­ FEBRUARY 2010 ­ REVISED OCTOBER 2010 www. ti. com · · · · · ­ End Point 0 (Control) ­ End Points 1, 2, 3, 4 (Control, Bulk, Interrupt or ISOC) Rx and Tx Two Multichannel Audio Serial Ports: ­ Six Clock Zones and 28 Serial Data Pins ­ Supports TDM, I2S, and Similar Formats ­ FIFO buffers for Transmit and Receive 10/100 Mb/s Ethernet MAC (EMAC): ­ IEEE 802. 3 Compliant (3. 3-V I/O Only) ­ RMII Media Independent Interface ­ Management Data I/O (MDIO) Module One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers) One 64-bit General-Purpose/Watchdog Timer (Configurable as Two 32-bit General-Purpose Timers) Three Enhanced Pulse Width Modulators (eHRPWM): ­ Dedicated 16-Bit Time-Base Counter With Period And Frequency Control · · · · · ­ 6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs ­ Dead-Band Generation ­ PWM Chopping by High-Frequency Carrier ­ Trip Zone Input Three 32-Bit Enhanced Capture Modules (eCAP): ­ Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator (APWM) outputs ­ Single Shot Capture of up to Four Event Time-Stamps Two 32-Bit Enhanced Quadrature Encoder Pulse Modules (eQEP) 176-pin PowerPADTM Plastic Quad Flat Pack [PTP suffix], 0. 5-mm Pin Pitch Commercial, Industrial, or Extended Temperature Community Resources ­ TI E2E Community ­ TI Embedded Processors Wiki ADVANCE INFORMATION 2 AM1705 ARM Microprocessor Submit Documentation Feedback Product Folder Link(s): AM1705 Copyright © 2010, Texas Instruments Incorporated AM1705 www. ti. com SPRS657B ­ FEBRUARY 2010 ­ REVISED OCTOBER 2010 1. 2 Trademarks All trademarks are the property of their respective owners. Copyright © 2010, Texas Instruments Incorporated AM1705 ARM Microprocessor Submit Documentation Feedback Product Folder Link(s): AM1705 3 ADVANCE INFORMATION AM1705 SPRS657B ­ FEBRUARY 2010 ­ REVISED OCTOBER 2010 www. ti. com 1. 3 Description The device is a low-power ARM microprocessor based on an ARM926EJ-STM. [. . . ] In the case where the master SPI is ready with new data before SPI0_SCS assertion. This delay can be increased under software control by the register bit field SPIDELAY. C2TDELAY[4:0]. Except for modes when SPIDAT1. CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain asserted. This delay can be increased under software control by the register bit field SPIDELAY. T2CDELAY[4:0]. Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): AM1705 101 ADVANCE INFORMATION These parameters are in addition to the general timings for SPI master modes (Table 6-49). P = SYSCLK2 period Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes. In the case where the master SPI is ready with new data before SPI0_ENA assertion. In the case where the master SPI is ready with new data before SPI0_EN A deassertion. AM1705 SPRS657B ­ FEBRUARY 2010 ­ REVISED OCTOBER 2010 www. ti. com (3) Table 6-53. Additional (1) SPI0 Master Timings, 5-Pin Option (2) No. PARAMETER Polarity = 0, Phase = 0, from SPI0_CLK falling Max delay for slave to deassert SPI0_ENA after final SPI0_CLK edge to ensure master does not begin the next transfer. (4) Polarity = 0, Phase = 1, from SPI0_CLK falling Polarity = 1, Phase = 0, from SPI0_CLK rising Polarity = 1, Phase = 1, from SPI0_CLK rising Polarity = 0, Phase = 0, from SPI0_CLK falling Delay from final SPI0_CLK edge to master deasserting SPI0_SCS (5) (6) Polarity = 0, Phase = 1, from SPI0_CLK falling Polarity = 1, Phase = 0, from SPI0_CLK rising Polarity = 1, Phase = 1, from SPI0_CLK rising 21 Max delay for slave SPI to drive SPI0_ENA valid td(SCSL_ENAL)M after master asserts SPI0_SCS to delay the master from beginning the next transfer, Polarity = 0, Phase = 0, to SPI0_CLK rising Delay from SPI0_SCS active to first SPI0_CLK (7) (8) (9) Polarity = 0, Phase = 1, to SPI0_CLK rising Polarity = 1, Phase = 0, to SPI0_CLK falling Polarity = 1, Phase = 1, to SPI0_CLK falling Polarity = 0, Phase = 0, to SPI0_CLK rising Delay from assertion of SPI0_ENA low to first SPI0_CLK edge. (10) Polarity = 0, Phase = 1, to SPI0_CLK rising Polarity = 1, Phase = 0, to SPI0_CLK falling Polarity = 1, Phase = 1, to SPI0_CLK falling (1) (2) (3) (4) (5) 2P -5 0. 5tc(SPC)M + 2P -5 0. 5tc(SPC)M + P - 3 P-3 MIN MAX 0. 5tc(SPC)M + P + 5 P+5 UNIT 18 td(SPC_ENA)M ns 0. 5tc(SPC)M + P + 5 P+5 20 td(SPC_SCS)M ns 0. 5tc(SPC)M + P -3 P-3 C2TDELAY + P ns ADVANCE INFORMATION 22 td(SCS_SPC)M ns 2P -5 0. 5tc(SPC)M + 2P -5 3P + 3 0. 5tc(SPC)M + 3P + 3 ns 3P + 3 0. 5tc(SPC)M + 3P + 3 23 td(ENA_SPC)M These parameters are in addition to the general timings for SPI master modes (Table 6-50). P = SYSCLK2 period Figure shows only Polarity = 0, Phase = 0 as an example. Table gives parameters for all four master clocking modes. In the case where the master SPI is ready with new data before SPI0_ENA deassertion. Except for modes when SPIDAT1. CSHOLD is enabled and there is additional data to transmit. In this case, SPI0_SCS will remain asserted. (6) This delay can be increased under software control by the register bit field SPIDELAY. T2CDELAY[4:0]. (7) If SPI0_ENA is asserted immediately such that the transmission is not delayed by SPI0_ENA. (8) In the case where the master SPI is ready with new data before SPI0_SCS assertion. (9) This delay can be increased under software control by the register bit field SPIDELAY. C2TDELAY[4:0]. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]