User manual TEXAS INSTRUMENTS OMAP-L138 ADVANCE INFORMATION 08-2010

[. . . ] OMAP-L138 www. ti. com SPRS586B ­ JUNE 2009 ­ REVISED AUGUST 2010 OMAP-L138 Low-Power Applications Processor Check for Samples: OMAP-L138 1 OMAP-L138 Low-Power Applications Processor 1. 1 123 Features ­ Normalization, Saturation, Bit-Counting ­ Compact 16-Bit Instructions · C674x Two Level Cache Memory Architecture ­ 32K-Byte L1P Program RAM/Cache ­ 32K-Byte L1D Data RAM/Cache ­ 256K -Byte L2 Unified Mapped RAM/Cache ­ Flexible RAM/Cache Partition (L1 and L2) · Enhanced Direct-Memory-Access Controller 3 (EDMA3): ­ 2 Channel Controllers ­ 3 Transfer Controllers ­ 64 Independent DMA Channels ­ 16 Quick DMA Channels ­ Programmable Transfer Burst Size · TMS320C674x Floating-Point VLIW DSP Core ­ Load-Store Architecture With Non-Aligned Support ­ 64 General-Purpose Registers (32 Bit) ­ Six ALU (32-/40-Bit) Functional Units · Supports 32-Bit Integer, SP (IEEE Single Precision/32-Bit) and DP (IEEE Double Precision/64-Bit) Floating Point · Supports up to Four SP Additions Per Clock, Four DP Additions Every 2 Clocks · Supports up to Two Floating Point (SP or DP) Reciprocal Approximation (RCPxP) and Square-Root Reciprocal Approximation (RSQRxP) Operations Per Cycle ­ Two Multiply Functional Units · Mixed-Precision IEEE Floating Point Multiply Supported up to: ­ 2 SP x SP -> SP Per Clock ­ 2 SP x SP -> DP Every Two Clocks ­ 2 SP x DP -> DP Every Three Clocks ­ 2 DP x DP -> DP Every Four Clocks · Fixed Point Multiply Supports Two 32 x 32-Bit Multiplies, Four 16 x 16-Bit Multiplies, or Eight 8 x 8-Bit Multiplies per Clock Cycle, and Complex Multiples ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional · Highlights ­ Dual Core SoC · 375/456-MHz ARM926EJ-STM RISC MPU · 375/456-MHz C674x Fixed/Floating-Point VLIW DSP ­ Enhanced Direct-Memory-Access Controller (EDMA3) ­ Serial ATA (SATA) Controller ­ DDR2/Mobile DDR Memory Controller ­ Two Multimedia Card (MMC)/Secure Digital (SD) Card Interface ­ LCD Controller ­ Video Port Interface (VPIF) ­ 10/100 Mb/s Ethernet MAC (EMAC): ­ Programmable Real-Time Unit Subsystem ­ Three Configurable UART Modules ­ USB 1. 1 OHCI (Host) With Integrated PHY ­ USB 2. 0 OTG Port With Integrated PHY ­ One Multichannel Audio Serial Port ­ Two Multichannel Buffered Serial Ports · Dual Core SoC ­ 375/456-MHz ARM926EJ-STM RISC MPU ­ 375/456-MHz C674x VLIW DSP · ARM926EJ-S Core ­ 32-Bit and 16-Bit (Thumb®) Instructions ­ DSP Instruction Extensions ­ Single Cycle MAC ­ ARM® Jazelle® Technology ­ EmbeddedICE-RTTM for Real-Time Debug · ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 16K-Byte Data Cache ­ 8K-Byte RAM (Vector Table) ­ 64K-Byte ROM · C674x Instruction Set Features ­ Superset of the C67x+TM and C64x+TM ISAs ­ Up to 3648/2746 C674x MIPS/MFLOPS ­ Byte-Addressable (8-/16-/32-/64-Bit Data) ­ 8-Bit Overflow Protection ­ Bit-Field Extract, Set, Clear 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TMS320C6000, C6000 are trademarks of Texas Instruments. ARM926EJ-S is a trademark of ARM Limited. Copyright © 2009­2010, Texas Instruments Incorporated ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. ADVANCE INFORMATION OMAP-L138 SPRS586B ­ JUNE 2009 ­ REVISED AUGUST 2010 www. ti. com · · · · · · · · · · · ­ Hardware Support for Modulo Loop Operation ­ Protected Mode Operation ­ Exceptions Support for Error Detection and Program Redirection Software Support ­ TI DSP/BIOSTM ­ Chip Support Library and DSP Library 128K-Byte RAM Shared Memory 1. 8V or 3. 3V LVCMOS IOs (except for USB and DDR2 interfaces) Two External Memory Interfaces: ­ EMIFA · NOR (8-/16-Bit-Wide Data) · NAND (8-/16-Bit-Wide Data) · 16-Bit SDRAM With 128 MB Address Space ­ DDR2/Mobile DDR Memory Controller · 16-Bit DDR2 SDRAM With 512 MB Address Space or · 16-Bit mDDR SDRAM With 256 MB Address Space Three Configurable 16550 type UART Modules: ­ With Modem Control Signals ­ 16-byte FIFO ­ 16x or 13x Oversampling Option LCD Controller Two Serial Peripheral Interfaces (SPI) Each With Multiple Chip-Selects Two Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO) Interfaces Two Master/Slave Inter-Integrated Circuit (I2C BusTM) One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High Bandwidth Programmable Real-Time Unit Subsystem (PRUSS) ­ Two Independent Programmable Realtime Unit (PRU) Cores · 32-Bit Load/Store RISC architecture · 4K Byte instruction RAM per core · 512 Bytes data RAM per core · PRU Subsystem (PRUSS) can be disabled via software to save power · Register 30 of each PRU is exported from the subsystem in addition to the normal R31 output of the PRU cores. [. . . ] Table 6-31 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note that this table only covers the bypass needs of the Soc and DDR2/mDDR interfaces. Additional bulk bypass capacitance may be needed for other circuitry. 1 2 3 4 5 6 (1) (2) Parameter DDR_DVDD18 Supply Bulk Bypass Capacitor Count DDR_DVDD18 Supply Bulk Bypass Total Capacitance DDR#1 Bulk Bypass Capacitor Count DDR#1 Bulk Bypass Total Capacitance DDR#2 Bulk Bypass Capacitor Count DDR#2 Bulk Bypass Total Capacitance Min 3 30 1 22 1 22 Max Unit Devices mF Devices mF Devices mF See Notes See Note (1) (2) Notes See Note See Note (1) (1) , (2) These devices should be placed near the device they are bypassing, but preference should be given to the placement of the high-speed (HS) bypass caps. Only used on dual-memory systems ADVANCE INFORMATION 6. 11. 3. 7 High-Speed Bypass Capacitors High-speed (HS) bypass capacitors are critical for proper DDR2/mDDR interface operation. It is particularly important to minimize the parasitic series inductance of the HS bypass cap, Soc /DDR2/mDDR power, and Soc /DDR2/mDDR ground connections. Table 6-32 contains the specification for the HS bypass capacitors as well as for the power connections on the PCB. 1 2 3 4 5 6 7 8 9 10 11 12 (1) (2) (3) (4) Parameter HS Bypass Capacitor Package Size Distance from HS bypass capacitor to device being bypassed Number of connection vias for each HS bypass capacitor Trace length from bypass capacitor contact to connection via Number of connection vias for each DDR2/mDDR device power or ground balls Trace length from DDR2/mDDR device power ball to connection via DDR_DVDD18 Supply HS Bypass Capacitor Count DDR_DVDD18 Supply HS Bypass Capacitor Total Capacitance DDR#1 HS Bypass Capacitor Count DDR#1 HS Bypass Capacitor Total Capacitance DDR#2 HS Bypass Capacitor Count DDR#2 HS Bypass Capacitor Total Capacitance 10 0. 6 8 0. 4 8 0. 4 2 1 1 35 30 Min Max 0402 250 Unit 10 Mils Mils Vias Mils Vias Mils Devices mF Devices mF Devices mF See Notes See Note (3) (4) Notes See Note See Note (1) (2) See Note See Note (3) (3) , (4) LxW, 10 mil units, i. e. , a 0402 is a 40x20 mil surface mount capacitor An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. These devices should be placed as close as possible to the device being bypassed. Only used on dual-memory systems 136 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): OMAP-L138 Copyright © 2009­2010, Texas Instruments Incorporated OMAP-L138 www. ti. com SPRS586B ­ JUNE 2009 ­ REVISED AUGUST 2010 6. 11. 3. 8 Net Classes Table 6-33 lists the clock net classes for the DDR2/mDDR interface. Table 6-34 lists the signal net classes, and associated clock net classes, for the signals in the DDR2/mDDR interface. These net classes are used for the termination and routing rules that follow. Clock Net Class Definitions Clock Net Class CK DQS0 DQS1 Soc Pin Names DDR_CLKP / DDR_CLKN DDR_DQS[0] DDR_DQS[1] Table 6-34. Signal Net Class Definitions Clock Net Class ADDR_CTRL D0 D1 DQGATE Associated Clock Net Class CK DQS0 DQS1 Soc Pin Names DDR_BA[2:0], DDR_A[13:0], DDR_CS, DDR_CAS, DDR_RAS, DDR_WE, DDR_CKE DDR_D[7:0], DDR_DQM0 DDR_D[15:8], DDR_DQM1 CK, DQS0, DQS1 DDR_DQGATE0, DDR_DQGATE1 6. 11. 3. 9 DDR2/mDDR Signal Termination No terminations of any kind are required in order to meet signal integrity and overshoot requirements. Serial terminators are permitted, if desired, to reduce EMI risk; however, serial terminations are the only type permitted. Table 6-35 shows the specifications for the series terminators. 1 2 3 4 (1) (2) (3) (4) Parameter CK Net Class ADDR_CTRL Net Class Data Byte Net Classes (DQS[0], DQS[1], D0, D1) DQGATE Net Class (DQGATE) Min 0 0 0 0 22 22 10 Typ Max 10 Zo Zo Zo Unit See Note Notes (1) (1) (2) (3) See Notes See Notes See Notes , , , , (1) (2) (3) (4) , , , (1) (2) (3) Only series termination is permitted, parallel or SST specifically disallowed. Terminator values larger than typical only recommended to address EMI issues. Termination value should be uniform across net class. When no termination is used on data lines (0 ), the DDR2/mDDR devices must be programmed to operate in 60% strength mode. Copyright © 2009­2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): OMAP-L138 137 ADVANCE INFORMATION OMAP-L138 SPRS586B ­ JUNE 2009 ­ REVISED AUGUST 2010 www. ti. com 6. 11. 3. 10 VREF Routing VREF is used as a reference by the input buffers of the DDR2/mDDR memories as well as the OMAP-L138 . VREF is intended to be half the DDR2/mDDR power supply voltage and should be created using a resistive divider as shown in Figure 6-18. Other methods of creating VREF are not recommended. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]