User manual TEXAS INSTRUMENTS SM320F28335-HT DATA MANUAL

[. . . ] SM320F28335-HT Digital Signal Controller (DSC) Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SPRS682 December 2010 SM320F28335-HT SPRS682 ­ DECEMBER 2010 www. ti. com Contents 1 2 3 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] The ADC module consists of a 12-bit ADC with a built-in sample-and-hold (S/H) circuit. Functions of the ADC module include: · 12-bit ADC core with built-in S/H · Analog input: 0. 0 V to 3. 0 V (Voltages above 3. 0 V produce full-scale conversion results. ) · Fast conversion rate: Up to 80 ns at 25-MHz ADC clock, 12. 5 MSPS · 16-channel, MUXed inputs · Autosequencing capability provides up to 16 "autoconversions" in a single session. Each conversion can be programmed to select any 1 of 16 input channels · Sequencer can be operated as two independent 8-state sequencers or as one large 16-state sequencer (i. e. , two cascaded 8-state sequencers) · Sixteen result registers (individually addressable) to store conversion values ­ The digital value of the input analog voltage is derived by: Digital Value + 0, Digital Value + 4096 Digital Value + 4095, A. All fractional values are truncated. when input 0 V Input Analog Voltage * ADCLO 3 when 0 V < input < 3 V when input 3 V · · · · · Multiple triggers as sources for the start-of-conversion (SOC) sequence ­ S/W - software immediate start ­ ePWM start of conversion ­ XINT2 ADC start of conversion Flexible interrupt control allows interrupt request on every end-of-sequence (EOS) or every other EOS. Sequencer can operate in "start/stop" mode, allowing multiple "time-sequenced triggers" to synchronize conversions. SOCA and SOCB triggers can operate independently in dual-sequencer mode. Sample-and-hold (S/H) acquisition time window has separate prescale control. The ADC module in the F28335 has been enhanced to provide flexible interface to ePWM peripherals. The ADC interface is built around a fast, 12-bit ADC module with a fast conversion rate of up to 80 ns at 25-MHz ADC clock. The ADC module has 16 channels, configurable as two independent 8-channel modules. The two independent 8-channel modules can be cascaded to form a 16-channel module. Although there are multiple input channels and two sequencers, there is only one converter in the ADC module. Figure 4-8 shows the block diagram of the ADC module. The two 8-channel modules have the capability to autosequence a series of conversions, each module has the choice of selecting any one of the respective eight channels available through an analog MUX. In the cascaded mode, the autosequencer functions as a single 16-channel sequencer. On each sequencer, once the conversion is complete, the selected channel value is stored in its respective RESULT register. Autosequencing allows the system to convert the same channel multiple times, allowing the user to perform oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results. 64 Peripherals Submit Documentation Feedback Product Folder Link(s): SM320F28335-HT Copyright © 2010, Texas Instruments Incorporated SM320F28335-HT www. ti. com SPRS682 ­ DECEMBER 2010 System Control Block HALT High-Speed Prescaler SYSCLKOUT DSP ADCENCLK Analog MUX ADCINA0 S/H ADCINA7 HSPCLK Result Registers Result Reg 0 Result Reg 1 70A8h 12-Bit ADC Module Result Reg 7 Result Reg 8 70AFh 70B0h ADCINB0 S/H ADCINB7 Result Reg 15 70B7h ADC Control Registers S/W EPWMSOCA GPIO/ XINT2_ADCSOC SOC Sequencer 1 Sequencer 2 SOC S/W EPWMSOCB Figure 4-8. Block Diagram of the ADC Module To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs. Furthermore, proper isolation techniques must be used to isolate the ADC module power pins ( VDD1A18, VDD2A18 , VDDA2, VDDAIO) from the digital supply. Figure 4-9 shows the ADC pin connections for the devices. The ADC registers are accessed at the SYSCLKOUT rate. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]