User manual TEXAS INSTRUMENTS STELLARIS LM3S1332 DATA SHEET REV D
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TEXAS INSTRUMENTS STELLARIS LM3S1332 DATA SHEET 9-04-2010 (4764 ko)
Manual abstract: user guide TEXAS INSTRUMENTS STELLARIS LM3S1332DATA SHEET REV D
Detailed instructions for use are in the User's Guide.
[. . . ] TE X AS I NS TRUM E NTS - P RO DUCTION D ATA
Stellaris® LM3S1332 Microcontroller
D ATA SH E E T
D S -LM 3S 1332 - 7 3 9 3
C opyri ght © 2007-2010 Texas Instruments Incorporated
Copyright
Copyright © 2007-2010 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. [. . . ] If read, the state of the previous mass erase access is provided. If the previous mass erase access is complete, a 0 is returned; otherwise, if the previous mass erase access is not complete, a 1 is returned. This can take up to 250 ms.
June 23, 2010 Texas Instruments-Production Data
151
Internal Memory
Bit/Field 1
Name ERASE
Type R/W
Reset 0
Description Erase a Page of Flash Memory If this bit is set, the page of flash main memory as specified by the contents of FMA is erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous erase access is provided. If the previous erase access is complete, a 0 is returned; otherwise, if the previous erase access is not complete, a 1 is returned. This can take up to 25 ms.
0
WRITE
R/W
0
Write a Word into Flash Memory If this bit is set, the data stored in FMD is written into the location as specified by the contents of FMA. A write of 0 has no effect on the state of this bit. If read, the state of the previous write update is provided. If the previous write access is complete, a 0 is returned; otherwise, if the write access is not complete, a 1 is returned. This can take up to 50 µs.
152 Texas Instruments-Production Data
June 23, 2010
Stellaris® LM3S1332 Microcontroller
Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C
This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled if the corresponding FCIM register bit is set.
Flash Controller Raw Interrupt Status (FCRIS)
Base 0x400F. D000 Offset 0x00C Type RO, reset 0x0000. 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 PRIS RO 0 RO 0 0 ARIS RO 0
Bit/Field 31:2
Name reserved
Type RO
Reset 0x0
Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Raw Interrupt Status This bit provides status on programming cycles which are write or erase actions generated through the FMC register bits (see page 151). Value Description 1 0 The programming cycle has completed. The programming cycle has not completed.
1
PRIS
RO
0
This status is sent to the interrupt controller when the PMASK bit in the FCIM register is set. This bit is cleared by writing a 1 to the PMISC bit in the FCMISC register. 0 ARIS RO 0 Access Raw Interrupt Status Value Description 1 A program or erase action was attempted on a block of Flash memory that contradicts the protection policy for that block as set in the FMPPEn registers. No access has tried to improperly program or erase the Flash memory.
0
This status is sent to the interrupt controller when the AMASK bit in the FCIM register is set. This bit is cleared by writing a 1 to the AMISC bit in the FCMISC register.
June 23, 2010 Texas Instruments-Production Data
153
Internal Memory
Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010
This register controls whether the flash controller generates interrupts to the controller.
Flash Controller Interrupt Mask (FCIM)
Base 0x400F. D000 Offset 0x010 Type R/W, reset 0x0000. 0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved Type Reset RO 0 15 RO 0 14 RO 0 13 RO 0 12 RO 0 11 RO 0 10 RO 0 9 reserved Type Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 8 RO 0 7 RO 0 6 RO 0 5 RO 0 4 RO 0 3 RO 0 2 RO 0 1 PMASK R/W 0 RO 0 0 AMASK R/W 0
Bit/Field 31:2
Name reserved
Type RO
Reset 0x0
Description Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. Programming Interrupt Mask This bit controls the reporting of the programming raw interrupt status to the interrupt controller. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]
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