User manual TEXAS INSTRUMENTS TMS320C5514 DATASHEET 08-2010

[. . . ] TMS320C5514 www. ti. com SPRS646B ­ AUGUST 2010 ­ REVISED AUGUST 2010 TMS320C5514 Fixed-Point Digital Signal Processor Check for Samples: TMS320C5514 1 Fixed-Point Digital Signal Processor 1. 1 12 Features ­ Industrial Temperature Devices Available · 256K Bytes Zero-Wait State On-Chip RAM, Composed of: ­ 64K Bytes of Dual-Access RAM (DARAM), 8 Blocks of 4K x 16-Bit ­ 192K Bytes of Single-Access RAM (SARAM), 24 Blocks of 4K x 16-Bit · 128K Bytes of Zero Wait-State On-Chip ROM (4 Blocks of 16K x 16-Bit) · 4M x 16-Bit Maximum Addressable External Memory Space (SDRAM/mSDRAM) · 16-/8-Bit External Memory Interface (EMIF) with Glueless Interface to: ­ 8-/16-Bit NAND Flash, 1- and 4-Bit ECC ­ 8-/16-Bit NOR Flash ­ Asynchronous Static RAM (SRAM) ­ SDRAM/mSDRAM (1. 8-, 2. 5-, 2. 75-, and 3. 3-V) · Direct Memory Access (DMA) Controller ­ Four DMA With 4 Channels Each (16-Channels Total) · Three 32-Bit General-Purpose Timers ­ One Selectable as a Watchdog and/or GP · Two MultiMedia Card/Secure Digital (MMC/SD) Interfaces · Universal Asynchronous Receiver/Transmitter (UART) · Serial-Port Interface (SPI) With Four Chip-Selects · Master/Slave Inter-Integrated Circuit (I2C BusTM) · Four Inter-IC Sound (I2S BusTM) for Data Transport · HIGHLIGHTS: · High-Perf/Low-Power, C55xTM Fixed-Point DSP ­ 16. 67/13. 33/10/8. 33-ns Instruction Cycle Time ­ 60-, 75-, 100-, 120-MHz Clock Rate · 256K Bytes On-Chip RAM · 16-/8-Bit External Memory Interface (EMIF) · Two MultiMedia Card/Secure Digital I/Fs · Serial-Port I/F (SPI) With Four Chip-Selects · Four Inter-IC Sound (I2S BusTM) · USB 2. 0 Full- and High-Speed Device · Real-Time Clock (RTC) With Crystal Input · Four Core Isolated Power Supply Domains · Four I/O Isolated Power Supply Domains · Three Integrated LDOs · Industrial Temperature Devices Available · 1. 05-V Core, 1. 8/2. 5/2. 75/3. 3-V I/Os · 1. 3-V Core, 1. 8/2. 5/2. 75/3. 3-V I/Os · FEATURES: · High-Performance, Low-Power, TMS320C55xTM Fixed-Point Digital Signal Processor ­ 16. 67-, 13. 33-, 10-, 8. 33-ns Instruction Cycle Time ­ 60-, 75-, 100-, 120-MHz Clock Rate ­ One/Two Instruction(s) Executed per Cycle ­ Dual Multipliers [Up to 200 or 240 Million Multiply-Accumulates per Second (MMACS)] ­ Two Arithmetic/Logic Units (ALUs) ­ Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses ­ Software-Compatible With C55x Devices 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320C5514 SPRS646B ­ AUGUST 2010 ­ REVISED AUGUST 2010 www. ti. com · Device USB Port With Integrated 2. 0 High-Speed PHY that Supports: ­ USB 2. 0 Full- and High-Speed Device · Real-Time Clock (RTC) With Crystal Input, With Separate Clock Domain, Separate Power Supply · Four Core Isolated Power Supply Domains: Analog, RTC, CPU and Peripherals, and USB · Four I/O Isolated Power Supply Domains: RTC I/O, EMIF I/O, USB PHY, and DVDDIO · Three integrated LDOs (DSP_LDO, ANA_LDO, and USB_LDO) to power the isolated domains: DSP Core, Analog, and USB Core, respectively · Low-Power S/W Programmable Phase-Locked Loop (PLL) Clock Generator · On-Chip ROM Bootloader (RBL) to Boot From NAND Flash, NOR Flash, SPI EEPROM, SPI Serial Flash or I2C EEPROM · IEEE-1149. 1 (JTAGTM) Boundary-Scan-Compatible · Up to 26 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) · 196-Terminal Pb-Free Plastic BGA (Ball Grid Array) (ZCH Suffix) · 1. 05-V Core (60 or 75 MHz), 1. 8-V, 2. 5-V, 2. 75-V, or 3. 3-V I/Os · 1. 3-V Core (100, 120 MHz), 1. 8-V, 2. 5-V, 2. 75-V, or 3. 3-V I/Os · Applications: ­ Wireless Audio Devices (e. g. , Headsets, Microphones, Speakerphones, etc. ) ­ Echo Cancellation Headphones ­ Portable Medical Devices ­ Voice Applications ­ Industrial Controls ­ Fingerprint Biometrics ­ Software Defined Radio · Community Resources ­ TI E2E Community ­ TI Embedded Processors Wiki 2 Fixed-Point Digital Signal Processor Submit Documentation Feedback Product Folder Link(s): TMS320C5514 Copyright © 2010, Texas Instruments Incorporated TMS320C5514 www. ti. com SPRS646B ­ AUGUST 2010 ­ REVISED AUGUST 2010 1. 2 Description The device is a member of TI's TMS320C5000TM fixed-point Digital Signal Processor (DSP) product family and is designed for low-power applications. [. . . ] The peripheral clock gating control registers (PCGCR1 and PCGCR2) are used to enable and disable peripheral clocks. The peripheral software reset counter register (PSRCR) and the peripheral reset control register (PRCR) are used to assert and de-assert peripheral reset signals. At hardware reset, all of the peripheral clocks are off to conserve power. After hardware reset, the DSP boots via the bootloader code in ROM. During the boot process, the bootloader queries each peripheral to determine if it can boot from that peripheral. In other words, it reads each peripheral looking for a valid boot image file. At that time, the individual peripheral clocks will be enabled for the query and then disabled again when the bootloader is finished with the peripheral. By the time the bootloader releases control to the user code, all peripheral clocks will be off and all domains in the ICR, except the CPU domain, will be idled. 4. 3. 1. 3 USB Oscillator Control The USB oscillator is controlled through the USB system control register (USBSCR). To enable the oscillator, the USBOSCDIS and USBOSCBIASDIS bits must be cleared to 0. The user must wait until the USB oscillator stabilizes before proceeding with the USB configuration. The USB oscillator stabilization time is typically 100 ms, with a 10 ms maximum (Note: the startup time is highly dependent on the ESR and capacitive load on the crystal). 46 Device Configuration Submit Documentation Feedback Product Folder Link(s): TMS320C5514 Copyright © 2010, Texas Instruments Incorporated TMS320C5514 www. ti. com SPRS646B ­ AUGUST 2010 ­ REVISED AUGUST 2010 4. 4 Boot Sequence The boot sequence is a process by which the device's on-chip memory is loaded with program and data sections from an external image file (in flash memory, for example). The boot sequence also allows, optionally, for some of the device's internal registers to be programmed with predetermined values. The boot sequence is started automatically after each device reset. For more details on device reset, see Section 6. 7, Reset. There are several methods by which the memory and register initialization can take place. Each of these methods is referred to as a boot mode. At reset, the device cycles through different boot modes until an image is found with a valid boot signature. The on-chip Bootloader allows the DSP registers to be configured during the boot process, if the optional register configuration section is present in the boot image (see Figure 4-3). For more information on the boot modes supported, see Section 4. 4. 1, Boot Modes. The device Bootloader follows the following steps as shown in Figure 4-3 1. Immediately after reset, the CPU fetches the reset vector from 0xFFFF00. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]