User manual TEXAS INSTRUMENTS TMS320C6457 DATA MANUAL REV B

[. . . ] TMS320C6457 Communications Infrastructure Digital Signal Processor Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SPRS582B July 2010 TMS320C6457 Data Manual SPRS582B--July 2010 www. ti. com Release History Additions/Modifications/Deletions SPRS582B · Added 850 mHz clock speed. · Added content to the Warm Reset section describing how to preserve contents of DDR2 SDRAM through a Warm Reset cycle with Self-Refresh mode enabled on the SDRAM. [. . . ] 3 These addresses correspond to the L1D memory protection page attribute registers 0-15 (L1DMPPA0 - L1DMPPA15) of the C64x+ Megamodule. These registers are not supported for the C6457 device. Table 5-13 CPU Megamodule Bandwidth Management Registers Acronym EMCCPUARBE EMCIDMAARBE EMCSDMAARBE EMCMDMAARBE L2DCPUARBU L2DIDMAARBU L2DSDMAARBU L2DUCARBU L1DCPUARBD L1DIDMAARBD L1DSDMAARBD L1DUCARBD Register Name EMC CPU Arbitration Control Register EMC IDMA Arbitration Control Register EMC Slave DMA Arbitration Control Register EMC Master DMA Arbitration Control Register Reserved L2D CPU Arbitration Control Register L2D IDMA Arbitration Control Register L2D Slave DMA Arbitration Control Register L2D User Coherence Arbitration Control Register Reserved L1D CPU Arbitration Control Register L1D IDMA Arbitration Control Register L1D Slave DMA Arbitration Control Register L1D User Coherence Arbitration Control Register Hex Address Range 0182 0200 0182 0204 0182 0208 0182 020C 0182 0210 - 0182 02FF 0184 1000 0184 1004 0184 1008 0184 100C 0184 1010 - 0184 103F 0184 1040 0184 1044 0184 1048 0184 104C End of Table 5-13 2009 Texas Instruments Incorporated C64x+ Megamodule 85 PRODUCT PREVIEW L1D memory protection page attribute register 27 TMS320C6457 Communications Infrastructure Digital Signal Processor SPRS582B--July 2010 www. ti. com PRODUCT PREVIEW 86 C64x+ Megamodule 2009 Texas Instruments Incorporated TMS320C6457 Communications Infrastructure Digital Signal Processor www. ti. com SPRS582B--July 2010 6 Device Operating Conditions Based on JESD22-C101C (Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components), the TMS320C6457 device's charged-device model (CDM) sensitivity classification is Class II (200 V to < 500 V). Specifically, DDR memory interface and SerDes pins conform to ±200-V level. All other pins conform to ±500 V. 6. 1 Absolute Maximum Ratings Table 6-1 Absolute Maximum Ratings (1) CVDD DVDD18 DVDD33 Supply voltage range (2): VREFSSTL VDD11, VDDD11, VDDT11 VDDR18 AVDD118, AVDD218 VSS Ground LVCMOS (1. 8V) LVCMOS (3. 3V) DDR2 Input voltage (VI) range: IC LVDS LJCB SerDes LVCMOS (1. 8V) LVCMOS (3. 3V) Output voltage (VO) range: DDR2 IC SerDes 850 MHz CPU Commercial Operating case temperature range, TC: Extended LVCMOS (1. 8V) Overshoot/undershoot (3) LVCMOS (3. 3V) DDR2 I2C Storage temperature range, Tstg: End of Table 6-1 1 Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 All voltage values are with respect to VSS. 3 Overshoot/Undershoot percentage relative to I/O operating values - for example the maximum overshoot value for 1. 8-V LVCMOS signals is DVDD18 + 0. 20 × DVDD18 and maximum undershoot value would be VSS - 0. 20 × DVDD18 2 2 Over Operating Case Temperature Range (Unless Otherwise Noted) -0. 3 V to 1. 35 V -0. 3 V to 2. 45 V 0. 49 × DVDD18 to 0. 51 × DVDD18 -0. 3 V to 1. 35 V -0. 3 V to 2. 45 V -0. 3 V to 2. 45 V 0V -0. 3 V to DVDD18 + 0. 3 V -0. 3 V to DVDD33 + 0. 3 V -0. 3 V to 2. 45 V -0. 3 V to 2. 45 V -0. 3 V to DVDD18 + 0. 3 V -0. 3 V to 1. 35 V -0. 3 V to DVDD11 + 0. 3 V -0. 3 V to DVDD18 + 0. 3 V -0. 3 V to DVDD33 + 0. 3 V -0. 3 V to 2. 45 V -0. 3 V to 2. 45 V -0. 3 V to DVDD11 + 0. 3 V 0°C to 100°C 0°C to 100°C 0°C to 95°C -40°C to 100°C -40°C to 95°C 1-GHz CPU 1. 2-GHz CPU 1-GHz CPU 1. 2-GHz CPU 20% Overshoot/Undershoot for 20% of Signal Duty Cycle -65°C to 150°C 2009 Texas Instruments Incorporated Device Operating Conditions 87 PRODUCT PREVIEW -0. 3 V to 3. 60V TMS320C6457 Communications Infrastructure Digital Signal Processor SPRS582B--July 2010 www. ti. com 6. 2 Recommended Operating Conditions Table 6-2 Recommended Operating Conditions (1) (2) Min 850-MHz CPU CVDD DVDD18 DVDD33 VREFSSTL VDDR18 VDDA11 Supply core voltage 1-GHz CPU 1. 2-GHz CPU 1. 8-V supply I/O voltage 3. 3-V supply I/O voltage DDR2 reference voltage SRIO/SGMII SerDes regulator supply SRIO/SGMII SerDes analog supply SRIO/SGMII SerDes digital supply SRIO/SGMII SerDes termination supply PLL1 analog supply PLL2 analog supply Ground LVCMOS (1. 8 V) VIH High-level input voltage LVCMOS (3. 3 V) IC DDR2 EMIF LVCMOS (1. 8 V) VIL Low-level input voltage LVCMOS (3. 3 V) DDR2 EMIF I2C 850 MHz CPU Commercial TC Operating case temperature Extended End of Table 6-2 1-GHz CPU 1. 2-GHz CPU 1-GHz CPU 1. 2-GHz CPU 0 0 0 -40 -40 -0. 3 2 Nom 1. 1 1. 1 1. 2 1. 8 3. 3 0. 5 × DVDD18 1. 8 1. 1 1. 1 1. 1 1. 8 1. 8 0 Max Unit 1. 133 1. 133 1. 236 1. 89 3. 465 0. 51 × DVDD18 1. 89 1. 155 1. 155 1. 155 1. 89 1. 89 0 V V V V V V V V V V V V V DVDD18 + 0. 3 0. 35 × DVDD18 0. 8 VREFSSTL - 0. 1 0. 3 × DVDD18 100 100 95 100 95 °C °C V V V V V V 1. 067 1. 067 1. 164 1. 71 3. 135 0. 49 × DVDD18 1. 71 1. 045 1. 045 1. 045 1. 71 1. 71 0 0. 65 × DVDD18 2. 0 0. 7 × DVDD18 VREFSSTL + 0. 125 PRODUCT PREVIEW VDDD11 VDDT11 PLLV1 PLLV2 VSS 1 All differential clock inputs comply with the LVDS Electrical Specification, IEEE 1596. 3-1996 and all SerDes I/Os comply with the XAUI Electrical Specification, IEEE 802. 3ae-2002. 2 All SerDes I/Os comply with the XAUI Electrical Specification, IEEE 802. 3ae-2002. 88 Device Operating Conditions 2009 Texas Instruments Incorporated TMS320C6457 Communications Infrastructure Digital Signal Processor www. ti. com SPRS582B--July 2010 6. 3 Electrical Characteristics Table 6-3 Electrical Characteristics Parameter LVCMOS (1. 8 V) VOH High-level output voltage LVCMOS (3. 3 V) DDR2 IC LVCMOS (1. 8 V) VOL Low-level output voltage LVCMOS (3. 3 V) DDR2 I2 C IO = 3 mA, pulled up to 1. 8 V No IPD/IPU LVCMOS (1. 8 V) Internal pullup Internal pulldown II (2) 2 Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted) Test Conditions IO = IOH IO = -2 mA (1) Min DVDD18 - 0. 45 2. 4 1. 4 0. 1 × DVDD18 Typ Max Unit V IO = IOL IO = 2 mA 0. 45 0. 4 0. 4 0. 4 -5 50 -170 -1 70 -270 -20 150 -150 100 -100 5 170 -50 1 270 -70 20 -8 -6 mA -4 4 -4 8 6 mA 4 -4 4 -20 -20 20 20 A A A A V Input current [DC] LVCMOS (3. 3 V) No IPD/IPU Internal pullup Internal pulldown I2 C EMU[18:00], GPIO[15:0], TIMO[1:0] 0. 1 × DVDD18 V < VI < 0. 9 × DVDD18 V IOH SYSCLKOUT, TDO, CLKR0, CLKX0, DX0, FSR0, FSX0, CLKR1, CLKX1, High-level output current [DC] DX1, FSR1, FSX1, AECLKOUT RESETSTAT, MDIO, MDCLK DDR2 LVCMOS (3. 3 V), except AECLKOUT EMU[18:00], GPIO[15:0], TIM[1:0] SYSCLKOUT, TDO, CLKR0, CLKX0, DX0, FSR0, FSX0, CLKR1, CLKX1, DX1, FSR1, FSX1, AECLKOUT RESETSTAT, MDIO, MDCLK DDR2 LVCMOS (3. 3 V), except AECLKOUT IOL Low-level output current [DC] IOZ (3) Off-state output current [DC] LVCMOS (1. 8 V) LVCMOS (3. 3 V) End of Table 6-3 1 For test conditions shown as MIN, MAX, or TYP, use the appropriate value specified in the recommended operating conditions table. 2 II applies to input-only pins and bi-directional pins. For input-only pins, II indicates the input leakage current. For bi-directional pins, II includes input leakage current and off-state (Hi-Z) output leakage current. 3 IOZ applies to output-only pins, indicating off-state (Hi-Z) output leakage current. 2009 Texas Instruments Incorporated Device Operating Conditions 89 PRODUCT PREVIEW TMS320C6457 Communications Infrastructure Digital Signal Processor SPRS582B--July 2010 Table 6-4 Power Supply www. ti. com Power Supply to Peripheral I/O Mapping (1) (2) I/O Buffer Type Associated Peripheral CORECLK(P|N) PLL input buffers Over Recommended Ranges of Supply Voltage and Operating Case Temperature (Unless Otherwise Noted)2 CVDD Supply core voltage LJCB DDRREFCLK(N|P) PLL input buffers RIOSGMIICLK(N|P) SerDes PLL input buffers ALTCORECLK PLL input buffer ALTDDRCLK PLL input buffer POR/RESET input buffers LVCMOS (1. 8 V) DVDD18 1. 8-V supply I/O voltage All GPIO peripheral I/O buffer All McBSP0/McBSP1 peripheral I/O buffer All MDIO peripheral I/O buffer All Timer0/Timer1 peripheral I/O buffer NMI input buffers PRODUCT PREVIEW DDR2 (1. 8V) Open-drain (1. 8 V) All DDR2 memory controller peripheral I/O buffer All I C peripheral I/O buffer All EMIFA peripheral I/O buffer 2 DVDD33 VDDA11 3. 3-V supply I/O voltage LVCMOS (3. 3 V) ALL HPI peripheral I/O buffer ALL UTOPIA peripheral I/O buffer SRIO/SGMII SerDes analog supply CML SRIO/SGMII SerDes CML I/O buffer End of Table 6-4 1 Please note that this table does not attempt to describe all functions of all power supply terminals but only those whose purpose it is to power peripheral I/O buffers and clock input buffers. 2 Please see the TMS320TCI6484 and TMS320C6457 DSPs Hardware Design Guide (SPRAAV7) for more information about individual peripheral I/O. 90 Device Operating Conditions 2009 Texas Instruments Incorporated TMS320C6457 Communications Infrastructure Digital Signal Processor www. ti. com SPRS582B--July 2010 7 C64x+ Peripheral Information and Electrical Specifications This chapter describes the various peripherals on the TMS320C6457 DSP. Peripheral specific information, timing diagrams, electrical specifications and register memory maps are described in this chapter. 7. 1 Parameter Information This section describes the conditions used to capture the electrical data seen in this chapter. Figure 7-1 Test Load Circuit for AC Timing Measurements Tester Terminal Electronics Data Manual Timing Reference Point Transmission Line Zo = 50 W (see Note A) 4. 0 pF 1. 85 pF Output Under Test Device Terminal (see Note B) (A) The data manual provides timing at the device terminal. For output timing analysis, the tester terminal electronics and its transmission line effects must be taken into account. A transmission line with a delay of 2 ns can be used to produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to add or subtract the transmission line delay (2 ns) from the data sheet timings. (B) Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the device terminal. The load capacitance value stated is only for characterization and measurement of AC timing signals. This load capacitance value does not indicate the maximum load the device is capable of driving. 7. 1. 1 1. 8-V Signal Transition Levels All input and output timing parameters are referenced to 0. 9 V for both 0 and 1 logic levels. Figure 7-2 Input and Output Voltage Reference Levels for 1. 8-V AC Timing Measurements Vref = 0. 9 V All rise and fall transition timing parameters are reference to VIL MAX and VIH MIN for input clocks. Figure 7-3 Rise and Fall Transition Time Voltage Reference Levels Vref = VIH MIN (or VOH MIN) 2009 Texas Instruments Incorporated C64x+ Peripheral Information and Electrical Specifications 91 PRODUCT PREVIEW 42 W 3. 5 nH TMS320C6457 Communications Infrastructure Digital Signal Processor SPRS582B--July 2010 www. ti. com 7. 1. 2 3. 3-V Signal Transition Levels All input and output timing parameters are referenced to 1. 5 V for both 0 and 1 logic levels. Figure 7-4 Input and Output Voltage Reference Levels for 3. 3-V AC Timing Measurements Vref = 1. 5 V All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks, VOL MAX and VOH MIN for output clocks. Figure 7-5 Rise and Fall Transition Time Voltage Reference Levels Vref = VIH MIN (or VOH MIN) PRODUCT PREVIEW 7. 1. 3 3. 3-V Signal Transition Rates All timings are tested with an input edge rate of 4 volts per nanosecond (4 V/ns). [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]