User manual TEXAS INSTRUMENTS TMS320C6672 DATA MANUAL 11-2010

[. . . ] TMS320C6672 Multicore Fixed and Floating-Point Digital Signal Processor Data Manual ADVANCE INFORMATION concerns new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice. Literature Number: SPRS708 November 2010 TMS320C6672 Data Manual SPRS708--November 2010 www. ti. com Release History Release 1. 0 Date November 2010 Chapter/Topic All Description/Comments Initial Release 2 Release History Copyright 2010 Texas Instruments Incorporated TMS320C6672 Multicore Fixed and Floating-Point Digital Signal Processor www. ti. com SPRS708--November 2010 Contents 1 Features . . 15 2. 1 2. 2 2. 3 2. 4 2. 5 Device Characteristics . . 25 Boot Modes Supported and PLL Settings . [. . . ] Although ramping DVDD18 and DVDD15 simultaneously is permitted, the voltage for DVDD15 must never exceed DVDD18. t2a t2b t2c t3 t4a 98 TMS320C6672 Peripheral Information and Electrical Specifications Copyright 2010 Texas Instruments Incorporated TMS320C6672 Multicore Fixed and Floating-Point Digital Signal Processor www. ti. com SPRS708--November 2010 POR-Controlled Power Sequencing -- Core Before IO (Part 2 of 2) System State · RESETFULL and RESET may be driven high anytime after DVDD18 is at a valid level. In a POR controlled boot both RESETFULL and RESET must be high before POR is driven high. · POR must continue to remain low for at least 100 s after power has stabilized. End Power Stabilization Phase · Device initialization requires 500 REFCLK periods after the Power Stabilization Phase. The maximum clock period is 33. 33 nsec, so a delay of an additional 16 s is required before a rising edge of POR. The clock must be active during the entire 16 s. · The rising edge of POR will remove the reset to the efuse farm, allowing the scan to begin. · Once device initialization and the efuse farm scan are complete, the RESETSTAT signal is driven high. This delay will be 10000 to 50000 clock cycles. Table 7-3 Time t4b t5 t6 t7 End of Table 7-3 7. 3. 1. 1. 2 IO-Before-Core Power Sequencing The timing diagram for IO-before-core power sequencing is shown in Figure 7-6 and defined in Table 7-4. Figure 7-6 POR-Controlled Power Sequencing -- IO Before Core Power Stabilization Phase PORz C hip Initialization Phase RESETF ULLz t2a R ESETz CVDD(core AVS) t2b CVD D1 (core constant) t1 DVDD18 (1. 8V) DVDD15 (1. 5V) t3b REFCLKP&N t3a t6 t4 t5 t3c t7 D DRCLKP&N RESETST ATz PORz Controlled Reset Sequencing ­ IO before Core Copyright 2010 Texas Instruments Incorporated TMS320C6672 Peripheral Information and Electrical Specifications 99 ADVANCE INFORMATION End Device Initialization Phase TMS320C6672 Multicore Fixed and Floating-Point Digital Signal Processor SPRS708--November 2010 Table 7-4 Time t1 www. ti. com POR-Controlled Power Sequencing -- IO Before Core System State Begin Power Stabilization Phase · DVDD18 (1. 8 V) supply is ramped up followed coincidentally by HHV (1. 8 V). · Since POR is low all the core logic having async reset (created from POR) are put into reset state once the core supply ramps. POR must remain low through Power Stabilization Phase. · Filtered versions of 1. 8V can ramp simultaneously with DVDD18. · RESETSTAT is driven low once the DVDD18 supply is available. · All input and bidirectional pins must not be driven or pulled high until DVDD18 is present. Driving an input or bidirectional pin before DVDD18 could cause damage to the device. · RESETFULL and RESET may be driven high anytime after DVDD18 is at a valid level. In a POR-controlled boot both RESETFULL and RESET must be high before POR is driven high. · CVDD1 (core constant) ramps at the same time or following CVDD. Although ramping CVDD1 and CVDD simultaneously is permitted the voltage for CVDD1 must never exceed CVDD until after CVDD has reached a valid voltage. · The purpose of ramping up the core supplies close to each other is to reduce crowbar current. CVDD1 (core constant) should trail CVDD (core AVS) as this will ensure that the WLs in the memories are turned off and there is no current through the memory bit cells. If, however, CVDD1 (core constant) ramps up before CVDD (core AVS) then the worst case current could be on the order of twice the specified draw of CVDD1. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]