User manual TEXAS INSTRUMENTS TMS320DM368 FEATURES 11-2010

[. . . ] TMS320DM368 www. ti. com SPRS668B ­ APRIL 2010 ­ REVISED NOVEMBER 2010 TMS320DM368 Digital Media System-on-Chip (DMSoC) Check for Samples: TMS320DM368 1 TMS320DM368 Digital Media System-on-Chip (DMSoC) 1. 1 12 Features device · ARM926EJ-STM Core ­ Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets ­ DSP Instruction Extensions and Single Cycle MAC ­ ARM® Jazelle® Technology ­ Embedded ICE-RT Logic for Real-Time Debug · ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 8K-Byte Data Cache ­ 32K-Byte RAM ­ 16K-Byte ROM ­ Little Endian · Two Video Image Co-processors (HDVICP, MJCP) Engines ­ Support a Range of Encode and Decode Operations ­ H. 264, MPEG4, MPEG2, MJPEG, JPEG, WMV9/VC1 · Video Processing Subsystem ­ Front End Provides: · HW Face Detect Engine · Hardware IPIPE for Real-Time Image Processing ­ Resize Engine ­ Resize Images From 1/16x to 8x ­ Separate Horizontal/Vertical Control ­ Two Simultaneous Output Paths · IPIPE Interface (IPIPEIF) · Image Sensor Interface (ISIF) and CMOS Imager Interface · 16-Bit Parallel AFE (Analog Front End) Interface Up to 120 MHz · Glueless Interface to Common Video Decoders · BT. 601/BT. 656/BT. 1120 Digital YCbCr 4:2:2 (8-/16-Bit) Interface · Histogram Module · Highlights ­ High-Performance Digital Media System-on-Chip (DMSoC) ­ 432-MHz ARM926EJ-S Clock Rate ­ Two Video Image Co-processors (HDVICP, MJCP) Engines ­ Supports a Range of Encode, Decode, and Video Quality Operations ­ Video Processing Subsystem · HW Face Detect Engine · Resize Engine from 1/16x to 8x · 16-Bit Parallel AFE (Analog Front-End) Interface Up to 120 MHz · 4:2:2 (8-/16-bit) Interface · 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output · 3 DACs for HD Analog Video Output · Hardware On-Screen Display (OSD) ­ Capable of 1080p 30fps H. 264 video processing ­ Peripherals include EMAC, USB 2. 0 OTG, DDR2/NAND, 5 SPIs, 2 UARTs, 2 MMC/SD/SDIO, Key Scan ­ 8 Different Boot Modes and Configurable Power-Saving Modes ­ Pin-to-pin and software compatible with DM365 ­ Extended temperature (-40ºC ­ 85ºC) available ­ 3. 3-V and 1. 8-V I/O, 1. 35-V Core ­ 338-Pin Ball Grid Array at 65nm Process Technology · High-Performance Digital Media System-on-Chip (DMSoC) ­ 432-MHz ARM926EJ-S Clock Rate ­ 4:2:2 (8-/16-Bit) Interface ­ Capable of 1080p 30fps H. 264 video processing ­ Pin compatible with DM365 processors ­ Fully Software-Compatible With ARM9TM ­ Extended temperature available for 432-Mhz 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320DM368 SPRS668B ­ APRIL 2010 ­ REVISED NOVEMBER 2010 www. ti. com · · · · · · · · · · · · Lens distortion correction module (LDC) ­ Back End Provides: · Hardware On-Screen Display (OSD) · Composite NTSC/PAL video encoder output · 8-/16-bit YCC and Up to 24-Bit RGB888 Digital Output · 3 DACs for HD Analog Video Output · LCD Controller · BT. 601/BT. 656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface Analog-to-Digital Convertor (ADC) Power Management and Real Time Clock Subsystem (PRTCSS) ­ Real Time Clock 16-Bit Host-Port Interface (HPI) 10/100 Mb/s Ethernet Media Access Controller (EMAC) - Digital Media ­ IEEE 802. 3 Compliant ­ Supports Media Independent Interface (MII) ­ Management Data I/O (MDIO) Module Key Scan Voice Codec External Memory Interfaces (EMIFs) ­ DDR2 and mDDR SDRAM 16-bit wide EMIF With 256 MByte Address Space (1. 8-V I/O) ­ Asynchronous16-/8-bit Wide EMIF (AEMIF) · Flash Memory Interfaces ­ NAND (8-/16-bit Wide Data) ­ 16 MB NOR Flash, SRAM ­ OneNAND(16-bit Wide Data) Flash Card Interfaces ­ Two Multimedia Card (MMC) / Secure Digital (SD/SDIO) ­ SmartMedia/xD Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels) USB Port with Integrated 2. 0 High-Speed PHY that Supports ­ USB 2. 0 High-Speed Device ­ USB 2. 0 High-Speed Host (mini-host, supporting one external device) ­ USB On The Go (HS-USB OTG) Four 64-Bit General-Purpose Timers (each configurable as two 32-bit timers) · One 64-Bit Watch Dog Timer · Two UARTs (One fast UART with RTS and CTS Flow Control) · Five Serial Port Interfaces (SPI) each with two Chip-Selects · One Master/Slave Inter-Integrated Circuit (I2C) BusTM · One Multi-Channel Buffered Serial Port (McBSP) ­ I2S ­ AC97 Audio Codec Interface ­ S/PDIF via Software ­ Standard Voice Codec Interface (AIC12) ­ SPI Protocol (Master Mode Only) ­ Direct Interface to T1/E1 Framers ­ Time Division Multiplexed Mode (TDM) ­ 128 Channel Mode · Four Pulse Width Modulator (PWM) Outputs · Four RTO (Real Time Out) Outputs · Up to 104 General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions) · Boot Modes ­ On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash, MMC/SD, UART, USB, SPI, EMAC, or HPI ­ AEMIF (NOR and OneNAND) · Configurable Power-Saving Modes · Crystal or External Clock Input (typically 19. 2 Mhz, 24 MHz, 27 Mhz or 36 MHz) · Flexible PLL Clock Generators · Debug Interface Support ­ IEEE-1149. 1 (JTAGTM) Boundary-Scan-Compatible ­ ETB (Embedded Trace Buffer) with 4K-Bytes Trace Buffer memory ­ Device Revision ID Readable by ARM · 338-Pin Ball Grid Array (BGA) Package (ZCE Suffix), 0. 65-mm Ball Pitch · 65nm Process Technology · 3. 3-V and 1. 8-V I/O, 1. 35-V Internal · Community Resources ­ TI E2E Community ­ TI Embedded Processors Wiki 2 TMS320DM368 Digital Media System-on-Chip (DMSoC) Submit Documentation Feedback Product Folder Link(s): TMS320DM368 Copyright © 2010, Texas Instruments Incorporated TMS320DM368 www. ti. com SPRS668B ­ APRIL 2010 ­ REVISED NOVEMBER 2010 1. 2 Description Developers can now deliver crystal clear multi-format video at up to 1080p H. 264 at 30fps (encode and closed-looped decode) in their digital video designs without concerns of video format support, constrained network bandwidth, limited system storage capacity or cost with the new TMS320DM368 DaVinciTM video processors from Texas Instruments Incorporated (TI). [. . . ] TI recommends no less than 8 small and 8 medium caps per supply be placed immediately next to the BGA vias, using the "interior" BGA space and at least the corners of the "exterior". Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order of 100 uF) should be furthest away, but still as close as possible. Large caps for each supply should be placed outside of the BGA footprint. Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of any component, verification of capacitor availability over the product's production lifetime should be considered. See also Section 6. 6. 1 for additional recommendations on power supplies for the oscillator/PLL supplies. Copyright © 2010, Texas Instruments Incorporated Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM368 79 TMS320DM368 SPRS668B ­ APRIL 2010 ­ REVISED NOVEMBER 2010 www. ti. com 6. 5 6. 5. 1 Reset Reset Electrical Data/Timing Table 6-2. Timing Requirements for Reset (1) (2) (3) (see Figure 6-4) DEVICE MIN MAX UNIT ns ns ns NO. 1 2 3 (1) (2) (3) tw(RESET) tsu(BOOT) th(BOOT) Active low width of the RESET pulse Setup time, boot configuration pins valid before RESET rising edge Hold time, boot configuration pins valid after RESET rising edge 12C 2E 0 BTSEL[2:0] and AECFG[2:0] are the boot configuration pins during device reset. For example, when MXI1/CLKIN frequency is 24 MHz use C = 41. 6 ns. E = 1/PLLC1SYSCLK4 cycle time in ns. 1 RESET 2 Boot Configuration Pins (BTSEL[2:0], AECFG[2:0]) 3 Figure 6-4. Reset Timing 80 Peripheral Information and Electrical Specifications Submit Documentation Feedback Product Folder Link(s): TMS320DM368 Copyright © 2010, Texas Instruments Incorporated TMS320DM368 www. ti. com SPRS668B ­ APRIL 2010 ­ REVISED NOVEMBER 2010 6. 6 Oscillators and Clocks The device has one oscillator input/output pair (MXI1/MXO1) usable with external crystals or ceramic resonators to provide clock inputs. The optimal frequencies for the crystals are 19. 2 MHz, 24 MHz, 27 MHz, and 36 MHz. Optionally, the oscillator inputs are configurable for use with external clock oscillators. If external clock oscillators are used, to minimize the clock jitter, a single clean power supply should power both the device and the external oscillator circuit and the minimum CLKIN rise and fall times must be observed. The electrical requirements and characteristics are described in this section. The timing parameters for CLKOUT[3:1] are also described in this section. The device has three output clock pins (CLKOUT[3:1]). See Section 3. 3 for more information on CLKOUT[3:1]. Note: Please ensure that the appropriate oscillator input pin (GIO81/OSCCFG) frequency range setting is set correctly. For more details on this pin setting, see Section 3. 7. 6. 6. 6. 1 MXI1 Oscillator The MXI1 (typically 24 MHz, can also be 19. 2 MHz, 27 MHz, or 36 MHz) oscillator provides the primary reference clock for the device. The on-chip oscillator requires an external crystal connected across the MXI1 and MXO1 pins, along with two load capacitors, as shown in Figure 6-5. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]