User manual TEXAS INSTRUMENTS TMS320DM6446 DATA MANUAL REV G

[. . . ] TMS320DM6446 www. ti. com SPRS283G ­ DECEMBER 2005 ­ REVISED JULY 2010 TMS320DM6446 Digital Media System-on-Chip Check for Samples: TMS320DM6446 1 Digital Media System-on-Chip (DMSoC) 1. 1 12 Features ­ 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative) ­ 64K-Byte L2 Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) ARM926EJ-S Core ­ Support for 32-Bit and 16-Bit (Thumb® Mode) Instruction Sets ­ DSP Instruction Extensions and Single Cycle MAC ­ ARM® Jazelle® Technology ­ EmbeddedICE-RTTM Logic for Real-Time Debug ARM9 Memory Architecture ­ 16K-Byte Instruction Cache ­ 8K-Byte Data Cache ­ 16K-Byte RAM ­ 8K-Byte ROM Embedded Trace BufferTM (ETB11TM) With 4KB Memory for ARM9 Debug Endianness: Little Endian for ARM and DSP Video Imaging Co-Processor (VICP) Video Processing Subsystem ­ Front End Provides: · CCD and CMOS Imager Interface · BT. 601/BT. 656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface · Preview Engine for Real-Time Image Processing · Glueless Interface to Common Video Decoders · Histogram Module · Auto-Exposure, Auto-White Balance and Auto-Focus Module · Resize Engine ­ Resize Images From 1/4x to 4x ­ Separate Horizontal/Vertical Control ­ Back End Provides: · Hardware On-Screen Display (OSD) · Four 54-MHz DACs for a Combination of ­ Composite NTSC/PAL Video ­ Luma/Chroma Separate Video · High-Performance Digital Media SoC ­ 513-, 594-, 810-MHz C64x+TM Clock Rates ­ 256. 5-, 297-, 405-MHz ARM926EJ-STM Clock Rates ­ Eight 32-Bit C64x+ Instructions/Cycle ­ 4104, 4752, 6480 C64x+ MIPS ­ Fully Software-Compatible With C64x / ARM9TM ­ Extended Temperature Devices Available · Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+TM DSP Core ­ Eight Highly Independent Functional Units · Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle · Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle ­ Load-Store Architecture With Non-Aligned Support ­ 64 32-Bit General-Purpose Registers ­ Instruction Packing Reduces Code Size ­ All Instructions Conditional ­ Additional C64x+TM Enhancements · Protected Mode Operation · Exceptions Support for Error Detection and Program Redirection · Hardware Support for Modulo Loop Operation · C64x+ Instruction Set Features ­ Byte-Addressable (8-/16-/32-/64-Bit Data) ­ 8-Bit Overflow Protection ­ Bit-Field Extract, Set, Clear ­ Normalization, Saturation, Bit-Counting ­ Compact 16-Bit Instructions ­ Additional Instructions to Support Complex Multiplies · C64x+ L1/L2 Memory Architecture ­ 32K-Byte L1P Program RAM/Cache (Direct Mapped) 1 · · · · · · 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. Copyright © 2005­2010, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. TMS320DM6446 SPRS283G ­ DECEMBER 2005 ­ REVISED JULY 2010 www. ti. com · · · · · · · · · (S-video) ­ Component (YPbPr or RGB) Video (Progressive) · Digital Output ­ 8-/16-bit YUV or up to 24-Bit RGB ­ HD Resolution ­ Up to 2 Video Windows External Memory Interfaces (EMIFs) ­ 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1. 8-V I/O) · Up to 167-MHz Controller (A-513, -594) · Up to 189-MHz Controller (-810) ­ Asynchronous16-Bit Wide EMIF (EMIFA) With 128M-Byte Address Reach · Flash Memory Interfaces ­ NOR (8-/16-Bit-Wide Data) ­ NAND (8-/16-Bit-Wide Data) Flash Card Interfaces ­ Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO) ­ Compact Flash Controller With True IDE Mode ­ SmartMedia Enhanced Direct-Memory-Access (EDMA3) Controller (64 Independent Channels) Two 64-Bit General-Purpose Timers (Each Configurable as Two 32-Bit Timers) One 64-Bit Watch Dog Timer Three UARTs (One with RTS and CTS Flow Control) One Serial Peripheral Interface (SPI) With Two Chip-Selects Master/Slave Inter-Integrated Circuit (I2C BusTM) Audio Serial Port (ASP) · · · · · · · · · · · · · · · · ­ I2S ­ AC97 Audio Codec Interface ­ Standard Voice Codec Interface (AIC12) 10/100 Mb/s Ethernet MAC (EMAC) ­ IEEE 802. 3 Compliant ­ Media Independent Interface (MII) VLYNQTM Interface (FPGA Interface) Host Port Interface (HPI) with 16-Bit Multiplexed Address/Data USB Port With Integrated 2. 0 PHY ­ USB 2. 0 High-/Full-Speed (480-Mbps) Client ­ USB 2. 0 High-/Full-/Low-Speed Host (Mini-Host, Supporting One External Device) Three Pulse Width Modulator (PWM) Outputs On-Chip ARM ROM Bootloader (RBL) to Boot From NAND Flash or UART ATA/ATAPI I/F (ATA/ATAPI-6 Specification) Individual Power-Saving Modes for ARM/DSP Flexible PLL Clock Generators IEEE-1149. 1 (JTAG) BoundaryScan-Compatible Up to 71 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions) 361-Pin Pb-Free BGA Package (ZWT Suffix), 0. 8-mm Ball Pitch 0. 09-mm/6-Level Cu Metal Process (CMOS) 3. 3-V and 1. 8-V I/O, 1. 2-V Internal (513, 594) 3. 3-V and 1. 8-V I/O, 1. 2-V DAC and USB, 1. 3-V Internal (810 only) Applications: ­ Digital Media ­ Networked Media Encode/Decode ­ Video Imaging 1. 2 Description The TMS320DM6446 (also referenced as DM6446) leverages TI's DaVinciTM technology to meet the networked media encode and decode application processing needs of next-generation embedded devices. [. . . ] If VLYNQ is enabled (VLYNQEN=1), VLYNQ_CLOCK, VLYNQ_TXD0, and VLYNQ_RXD0 are always selected. The VLYNQ_SCRUN function is only enabled if VLYNQEN=1 and VLSCREN=1 (VLSCREN overrides AECS4). The remaining VLYNQ TX/RX pins are selected based on the VLYNQWD value. Unselected VLYNQ TX/RX pins will function as either GPIO or EMIFA address based on the AEAW value. 78 Device Configurations Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 Copyright © 2005­2010, Texas Instruments Incorporated TMS320DM6446 www. ti. com SPRS283G ­ DECEMBER 2005 ­ REVISED JULY 2010 Table 3-23. VLYNQ Control, EMIFA, and GPIO Pin Multiplexing PINMUX0 REGISTER BIT FIELDS VLYNQEN 0 0 0 0 1 1 1 VLSCREN 0 0 1 AECS5 0 0 1 1 AECS4 0 1 0 1 0 1 MULTIPLEXED PINS EM_CS5/ GPIO[8]/ VLYNQ_CLOCK GPIO[8] GPIO[8] EM_CS5 EM_CS5 VLYNQ_CLOCK VLYNQ_CLOCK VLYNQ_CLOCK EM_CS4/ GPIO[9]/ VLYNQ_SCRUN GPIO[9] EM_CS4 GPIO[9] EM_CS4 GPIO[9] EM_CS4 VLYNQ_SCRUN Table 3-24. VLYNQ Data, EMIFA, and GPIO Pin Multiplexing PINMUX0 REGISTER BIT FIELDS VLYNQEN VLYNQWD EM_A[21]/ GPIO[10]/ VL_TXD0 EM_A[21]/ GPIO[10] (1) VL_TXD0 VL_TXD0 VL_TXD0 VL_TXD0 EM_A[20]/ GPIO[11]/ VL_RXD0 EM_A[20]/ GPIO[11] (1) VLRXD0 VLRXD0 VLRXD0 VLRXD0 EM_A[19]/ GPIO[12]/ VL_TXD1 EM_A[19]/ GPIO[12] (1) EM_A[19]/ GPIO[12] (1) VL_TXD1 VL_TXD1 VL_TXD1 MULTIPLEXED PINS EM_A[18]/ GPIO[13]/ VL_RXD1 EM_A[18]/ GPIO[13] (1) EM_A[18]/ GPIO[13] (1) VLRXD1 VLRXD1 VLRXD1 EM_A[17]/ GPIO[14]/ VL_TXD2 EM_A[17]/ GPIO[14] (1) EM_A[17]/ GPIO[14] (1) EM_A[17]/ GPIO[14] (1) VL_TXD2 VL_TXD2 EM_A[16]/ GPIO[15]/ VL_RXD2 EM_A[16]/ GPIO[15] (1) EM_A[16]/ GPIO[15] (1) EM_A[16]/ GPIO[15] (1) VLRXD2 VLRXD2 EM_A[15]/ GPIO[16]/ VL_TXD3 EM_A[15]/ GPIO[16] (1) EM_A[15]/ GPIO[16] (1) EM_A[15]/ GPIO[16] (1) EM_A[15]/ GPIO[16] (1) VL_TXD3 EM_A[14]/ GPIO[17]/ VL_RXD3 EM_A[14]/ GPIO[17] (1) EM_A[14]/ GPIO[17] (1) EM_A[14]/ GPIO[17] (1) EM_A[14]/ GPIO[17] (1) VLRXD3 0 1 1 1 1 00 01 10 11 (1) This pin shares GPIO functionality set by AEAW[4:0] as shown in Table 3-9. 3. 5. 6. 6 Timer0 Input, CLK_OUT1, and GPIO Pin Multiplexing The multiplexing of the CLK_OUT1 and Timer0 Input (Timer 0 only) functions is shown in Table 3-25. Timer0 Input, CLK_OUT1, and GPIO Pin Multiplexing PINMUX1 REGISTER BIT FIELDS TIMIN 0 0 1 CLK1 0 1 MULTIPLEXED PINS CLK_OUT1/ TIM_IN/ GPIO[49] GPIO[49] CLK_OUT1 TIM_IN 3. 5. 6. 7 ASP, SPI, I2C, ATA, and GPIO Pin Multiplexing When the ASP, SPI, or I2C serial port functions are not selected, their pins may be used as GPIOs as seen in Table 3-26, Table 3-27, and Table 3-28. The SPI_EN1 pin can also function as the HDDIR buffer control when ATAEN is selected and the HDIREN bit is set. ASP and GPIO Pin Multiplexing PINMUX1 REGISTER BIT FIELD ASP 0 CLKX/ GPIO[29] GPIO[29] CLKR/ GPIO[30] GPIO[30] MULTIPLEXED PINS FSX/ GPIO[31] GPIO[31] FSR/ GPIO[32] GPIO[32] DX/ GPIO[33] GPIO[33] DR/ GPIO[34] GPIO[34] 79 Copyright © 2005­2010, Texas Instruments Incorporated Device Configurations Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 TMS320DM6446 SPRS283G ­ DECEMBER 2005 ­ REVISED JULY 2010 www. ti. com Table 3-26. ASP and GPIO Pin Multiplexing (continued) PINMUX1 REGISTER BIT FIELD ASP 1 CLKX/ GPIO[29] CLKX CLKR/ GPIO[30] CLKR MULTIPLEXED PINS FSX/ GPIO[31] FSX FSR/ GPIO[32] FSR DX/ GPIO[33] DX DR/ GPIO[34] DR Table 3-27. SPI and GPIO Pin Multiplexing PINMUX0 AND PINMUX1 REGISTER BIT FIELDS SPI 0 0 0 0 1 1 1 1 ATAEN 0 0 1 1 0 0 1 1 HDIREN 0 1 0 1 0 1 0 1 SP_EN1/ HDDIR/ GPIO[42] GPIO[42] Driven Low GPIO[42] HDDIR SP_EN1 Driven Low SP_EN1 HDDIR MULTIPLEXED PINS SPI_DO/ GPIO[41] GPIO[41] GPIO[41] GPIO[41] GPIO[41] SPI_DO SPI_DO SPI_DO SPI_DO SPI_DI/ GPIO[40] GPIO[40] GPIO[40] GPIO[40] GPIO[40] SPI_DI SPI_DI SPI_DI SPI_DI SPI_CLK/ GPIO[39] GPIO[39] GPIO[39] GPIO[39] GPIO[39] SPI_CLK SPI_CLK SPI_CLK SPI_CLK SPI_EN0/ GPIO[37] GPIO[37] GPIO[37] GPIO[37] GPIO[37] SPI_EN0 SPI_EN0 SPI_EN0 SPI_EN0 Table 3-28. I2C and GPIO Pin Multiplexing PINMUX1 REGISTER BIT FIELD I2C 0 1 I2C_CLK/ GPIO[43] GPIO[43] I2C_CLK MULTIPLEXED PINS I2C_DATA/ GPIO[44] GPIO[44] I2C_DATA 3. 5. 6. 8 PWM, RGB888, and GPIO Pin Multiplexing Table 3-29 shows the PWM0/1/2 pin multiplexing. Each PWM output is independently controlled by its own enable bit. The PWM function has priority over RGB888 muxing (see Section 3. 5. 6. 3). PWM0/1/2, RGB888, and GPIO Pin Multiplexing PINMUX1 REGISTER BIT FIELDS PWM2 0 0 1 PWM1 0 0 1 PWM0 0 0 1 RGB888 0 1 PWM2/ B2/ GPIO[47] GPIO[47] B2 PWM2 MULTIPLEXED PINS PWM1/ R2/ GPIO[46] GPIO[46] R2 PWM1 PWM0/ GPIO[45] GPIO[45] GPIO[45] PWM0 - 3. 5. 6. 9 UART, VPFE, ATA, and GPIO Pin Multiplexing Each UART has independent pin multiplexing control bits in the PINMUX1 register. The UART2 peripheral may be used with or without the flow control signals. Table 3-30 shows how UART2 selection reduces the width of the VPFE interface. 80 Device Configurations Submit Documentation Feedback Product Folder Link(s): TMS320DM6446 Copyright © 2005­2010, Texas Instruments Incorporated TMS320DM6446 www. ti. com SPRS283G ­ DECEMBER 2005 ­ REVISED JULY 2010 Setting the UART1 bit enables UART1 transmit and receive pin functionality. Since these are shared with the ATA DMA handshake signals, enabling UART1 effectively disables the ATA DMA mode. However, ATA PIO mode is still supported with UART1 enabled. If the ATA module is not enabled, the pins are always configured for use by UART1. UART2, VPFE, and GPIO Pin Multiplexing PINMUX1 REGISTER BIT FIELDS UART2 0 1 1 (1) U2FLO 0 1 CCD[15]/ CI[7]/ UART_RXD2 CCD[15]/ CI[7] (1) UART_RXD2 UART_RXD2 MULTIPLEXED PINS CCD[14]/ CI[6]/ UART_TXD2 CCD[14]/ CI[6] (1) UART_TXD2 UART_TXD2 CCD[13]/ CI[5]/ UART_CTS2 CCD[13]/ CI[5] (1) CCD[13]/ CI[5] (1) UART_CTS2 CCD[12]/ CI[4]/ UART_RTS2 CCD[12]/ CI[4] (1) CCD[12]/ CI[4] (1) UART_RTS2 Functionality set by VPFE operating mode. Table 3-31. UART1 and ATA Pin Multiplexing PINMUX0 AND PINMUX1 REGISTER BIT FIELDS ATAEN 0 1 1 UART1 0 1 MULTIPLEXED PINS UART_TXD1/ DMACK UART_TXD1 DMACK UART_TXD1 UART_RXD1/ DMARQ UART_RXD1 DMARQ UART_RXD1 As Table 3-32 shows, the UART0 pins are configurable for either UART0 transmit and receive data functions or for GPIO. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]