User manual TEXAS INSTRUMENTS TVP5147M1 DATA MANUAL REV 12-2010

[. . . ] TVP5147M1 NTSC/PAL/SECAM 2 11-Bit Digital Video Decoder With MacrovisionTM Detection, YPbPr Inputs, and 5-Line Comb Filter Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SLES140F July 2005 ­ Revised December 2010 TVP5147M1 SLES140F ­ JULY 2005 ­ REVISED DECEMBER 2010 www. ti. com Contents 1 2 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1. 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] Reset Sequence SIGNAL NAME DURING RESET Input Input Input Output Input Output High impedance RESET COMPLETED High impedance Y[9:0], C[9:0] RESETB, PWDN, SDA, SCL, FSS, AVID, GLCO, HS, VS, FID INTREQ DATACLK POWER (3. 3 V and 1. 8 V) 1 ms (min) 200 ns (min) Normal Operation RESETB (Pin 34) Reset 1 ms (min) SDA (Pin 29) Invalid I 2C Cycle Valid Figure 2-18. Reset Timing The following register writes must be made before normal operation of the device. Copyright © 2005­2010, Texas Instruments Incorporated Functional Description Submit Documentation Feedback Product Folder Link(s): TVP5147M1 35 TVP5147M1 SLES140F ­ JULY 2005 ­ REVISED DECEMBER 2010 www. ti. com STEP 1 2 I2C SUBADDRESS 0x03 0x03 I2C DATA 0x01 0x00 When using the TVP5147M1I over the industrial (-40°C to 85°C) temperature range, the following register writes are required following device power up and RESETB to write 0x14 to VBUS register 0xA00014. This setup is optional when using the TVP5147M1 over the commercial (0°C to 70°C) temperature range. STEP 1 2 3 4 I2C SUBADDRESS 0xE8 0xE9 0xEA 0xE0 I2C DATA 0x14 0x00 0xA0 0x14 2. 9 Adjusting External Syncs The proper sequence to program the following external syncs is: · To set NTSC, PAL-M, NTSC 443, PAL60 (525-line modes): ­ Set the video standard to NTSC (register 02h). ­ Set HSYNC, VSYNC, VBLK, and AVID external syncs (registers 16h through 24h). · To set PAL, PAL-N, SECAM (625-line modes): ­ Set the video standard to PAL (register 02h). ­ Set HSYNC, VSYNC, VBLK, and AVID external syncs (registers 16h through 24h). · For autoswitch, set the video standard to autoswitch (register 02h). 36 Functional Description Submit Documentation Feedback Product Folder Link(s): TVP5147M1 Copyright © 2005­2010, Texas Instruments Incorporated TVP5147M1 www. ti. com SLES140F ­ JULY 2005 ­ REVISED DECEMBER 2010 2. 10 Internal Control Registers The TVP5147M1 decoder is initialized and controlled by a set of internal registers that define the operating parameters of the entire device. Communication between the external controller and the TVP5147M1 is through a standard I2C host port interface, as described earlier. Table 2-10 shows the summary of these registers. Detailed programming information for each register is described in the following sections. Additional registers are accessible through an indirect procedure involving access to an internal 24-bit address wide VBUS. Table 2-11 shows the summary of the VBUS registers. NOTE Do not write to reserved registers. Reserved bits in any defined register must be written with 0s, unless otherwise noted. Table 2-10. I2C Register Summary (1) REGISTER NAME Input select AFE gain control Video standard Operation mode Autoswitch mask Color killer Luminance processing control 1 Luminance processing control 2 Luminance processing control 3 Luminance brightness Luminance contrast Chrominance saturation Chroma hue Chrominance processing control 1 Chrominance processing control 2 Reserved AVID start pixel AVID stop pixel HSYNC start pixel HSYNC stop pixel VSYNC start line VSYNC stop line VBLK start line VBLK stop line Embedded Sync Offset Control 1 Embedded Sync Offset Control 2 Reserved Overlay delay Reserved CTI delay CTI control Reserved I2C SUBADDRESS 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh-15h 16h-17h 18h-19h 1Ah-1Bh 1Ch-1Dh 1Eh-1Fh 20h-21h 22h-23h 24h-25h 26h 27h 28h-2Ah 2Bh 2Ch 2Dh 2Eh 2Fh-31h 00h 00h R/W R/W 00h R/W 055h 325h 000h 040h 004h 007h 001h 015h 00h 00h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W DEFAULT 00h 0Fh 00h 00h 23h 10h 00h 00h 02h 80h 80h 80h 00h 00h 0Eh R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W (1) R = Read only, W = Write only, R/W = Read and write Reserved register addresses must not be written to. Functional Description Submit Documentation Feedback Product Folder Link(s): TVP5147M1 37 Copyright © 2005­2010, Texas Instruments Incorporated TVP5147M1 SLES140F ­ JULY 2005 ­ REVISED DECEMBER 2010 www. ti. com Table 2-10. I2C Register Summary (continued) REGISTER NAME Sync control Output formatter 1 Output formatter 2 Output formatter 3 Output formatter 4 Output formatter 5 Output formatter 6 Clear lost lock detect Status 1 Status 2 AGC gain status Reserved Video standard status GPIO input 1 GPIO input 2 Reserved AFE coarse gain for CH1 AFE coarse gain for CH2 AFE coarse gain for CH3 AFE coarse gain for CH4 AFE fine gain for Pb AFE fine gain for chroma AFE fine gain for Pr AFE fine gain for CVBS_Luma Reserved Field ID control Reserved F-bit and V-bit control 1 Reserved Back-end AGC control Reserved AGC decrement speed control ROM version RAM Version MSB Reserved AGC white peak processing F and V bit control VCR trick mode control Horizontal shake increment AGC increment speed AGC increment delay Reserved Analog output control 1 Chip ID MSB Chip ID LSB RAM Version LSB CPLL speed control 38 Functional Description Submit Documentation Feedback Product Folder Link(s): TVP5147M1 I2C SUBADDRESS 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch-3Dh 3Eh 3Fh 40h 41h 42h-45h 46h 47h 48h 49h 4Ah-4Bh 4Ch-4Dh 4Eh-4Fh 50h-51h 52h-56h 57h 58h-68h 69h 6Ah-6Bh 6Ch 6Dh-6Eh 6Fh 70h 71h 72h-73h 74h 75h 76h 77h 78h 79h 7Ah-7Eh 7Fh 80h 81h 82h 83h 09h 00h 51h 47h R/W R R R R/W 00h 12h 8Ah 64h 05h 1Eh R/W R/W R/W R/W R/W R/W 04h R/W R R 08h R/W 00h R/W 00h R/W 20h 20h 20h 20h 900h 900h 900h 900h R/W R/W R/W R/W R/W R/W R/W R/W R R R DEFAULT 00h 40h 00h FFh FFh FFh FFh 00h R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R Copyright © 2005­2010, Texas Instruments Incorporated TVP5147M1 www. ti. com SLES140F ­ JULY 2005 ­ REVISED DECEMBER 2010 Table 2-10. I2C Register Summary (continued) REGISTER NAME Reserved Status request Reserved Vertical line count Reserved AGC decrement delay Reserved VDP TTX filter 1 mask 1 VDP TTX filter 1 mask 2 VDP TTX filter 1 mask 3 VDP TTX filter 1 mask 4 VDP TTX filter 1 mask 5 VDP TTX filter 2 mask 1 VDP TTX filter 2 mask 2 VDP TTX filter 2 mask 3 VDP TTX filter 2 mask 4 VDP TTX filter 2 mask 5 VDP TTX filter control VDP FIFO word count VDP FIFO interrupt threshold Reserved VDP FIFO reset VDP FIFO output control VDP line number interrupt VDP pixel alignment Reserved VDP line start VDP line stop VDP global line mode VDP full field enable VDP full field mode Reserved VBUS data access with no VBUS address increment VBUS data access with VBUS address increment FIFO read data Reserved VBUS address access Reserved Interrupt raw status 0 Interrupt raw status 1 Interrupt status 0 Interrupt status 1 Interrupt mask 0 Interrupt mask 1 Interrupt clear 0 Interrupt clear 1 Reserved Copyright © 2005­2010, Texas Instruments Incorporated I2C SUBADDRESS 84h-96h 97h 98h-99h 9Ah-9Bh 9Ch-9Dh 9Eh 9Fh-B0h B1h B2h B3h B4h B5h B6h B7h B8h B9h BAh BBh BCh BDh BEh BFh C0h C1h C2h-C3h C4h-D5h D6h D7h D8h D9h DAh DBh-DFh E0h E1h E2h E3h-E7h E8h-EAh EBh-EFh F0h F1h F2h F3h F4h F5h F6h F7h F8h-FFh DEFAULT R/W 00h R/W R 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 00h 80h 00h 00h 00h 01Eh 06h 1Bh FFh 00h FFh 00h 00h R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R 00 0000h R/W R R R R 00h 00h 00h 00h R/W R/W R/W R/W Functional Description Submit Documentation Feedback Product Folder Link(s): TVP5147M1 39 TVP5147M1 SLES140F ­ JULY 2005 ­ REVISED DECEMBER 2010 www. ti. com Table 2-11. VBUS Register Summary (1) REGISTER NAME Reserved VDP closed caption data VDP WSS/CGMS data Reserved VDP VITC data Reserved VDP V-Chip data Reserved VDP general line mode and line address Reserved VDP VPS/Gemstar (PDC) data Reserved VDP FIFO read Reserved Analog output control 2 Reserved Interrupt configuration Reserved (1) I2C SUBADDRESS 00 0000h-80 051Bh 80 051Ch-80 051Fh 80 0520h-80 0526h 80 0527h-80 052Bh 80 052Ch-80 0534h 80 0535h-80 053Fh 80 0540h-80 0543h 80 0544h-80 05FFh 80 0600h-80 0611h 80 0612h-80 06FFh 80 0700h-80 070Ch 80 070Dh-90 1903h 90 1904h 90 1905h-A0 005Dh A0 05Eh A0 005Fh-B0 005Fh B0 0060h B0 0061h-FF FFFFh 00h R/W B2h R/W R R 00h, FFh R/W R R R R DEFAULT R/W Writing any value to a reserved register may cause erroneous operation of the TVP5147M1 decoder. It is recommended not to access any data to/from reserved registers. 40 Functional Description Submit Documentation Feedback Product Folder Link(s): TVP5147M1 Copyright © 2005­2010, Texas Instruments Incorporated TVP5147M1 www. ti. com SLES140F ­ JULY 2005 ­ REVISED DECEMBER 2010 2. 11 Register Definitions Table 2-12. Input Select Register Subaddress Default 7 00h 00h 6 5 4 3 Input select [7:0] 2 1 0 Ten input terminals can be configured to support composite, S-video, and component YPbPr as listed in Table 2-13. User must follow this table properly for S-video and component applications because only the terminal configurations listed in Table 2-13 are supported. Table 2-13. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]