User manual TEXAS INSTRUMENTS TVP5151 DATA MANUAL REV B

[. . . ] TVP5151 Ultralow-Power NTSC/PAL/SECAM Video Decoder Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Literature Number: SLES241B September 2009 ­ Revised June 2010 TVP5151 SLES241B ­ SEPTEMBER 2009 ­ REVISED JUNE 2010 www. ti. com Contents 1 2 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1. 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] An I2C master initiates a write operation to the TVP5151 decoder by generating a start condition (S) followed by the TVP5151 I2C slave address (see the following illustration), in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving an acknowledge from the TVP5151 decoder, the master presents the subaddress of the register, or the first of a block of registers it wants to write, followed by one or more bytes of data, MSB first. The TVP5151 decoder acknowledges each byte after completion of each transfer. The I2C master terminates the write operation by generating a stop condition (P). Step 1 I2C Start (master) Step 2 I2C slave address (master) Step 3 I2C Acknowledge (slave) Step 4 I C Write register address (master) Step 5 I2C Acknowledge (slave) Step 6 I2C Write data (master) Step 7 (1) I2C Acknowledge (slave) Step 8 I C Stop (master) (1) Repeat steps 6 and 7 until all data have been written. 2 2 0 S 7 1 9 A 7 Addr 9 A 7 Data 9 A 0 P 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 Data 6 Addr 5 Addr 4 Addr 3 Addr 2 Addr 1 Addr 0 Addr 6 0 5 1 4 1 3 1 2 0 1 X 0 0 3. 15. 2 I2C Read Operation The read operation consists of two phases. In this phase, an I2C master initiates a write operation to the TVP5151 decoder by generating a start condition (S) followed by the TVP5151 I2C slave address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving an acknowledge from the TVP5151 decoder, the master presents the subaddress of the register or the first of a block of registers it wants to read. After the cycle is acknowledged, the master terminates the cycle immediately by generating a stop condition (P). Read Address Selection I2CSEL 0 1 READ ADDRESS B9h BBh Copyright © 2009­2010, Texas Instruments Incorporated Functional Description Submit Documentation Feedback 25 TVP5151 SLES241B ­ SEPTEMBER 2009 ­ REVISED JUNE 2010 www. ti. com The second phase is the data phase. In this phase, an I2C master initiates a read operation to the TVP5151 decoder by generating a start condition followed by the TVP5151 I2C slave address (see the following illustration of a read operation), in MSB first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the TVP5151 decoder, the I2C master receives one or more bytes of data from the TVP5151 decoder. The I2C master acknowledges the transfer at the end of each byte. After the last data byte desired has been transferred from the TVP5151 decoder to the master, the master generates a not acknowledge followed by a stop. 3. 15. 2. 1 Read Phase 1 Step 1 I C Start (master) Step 2 I2C slave address (master) Step 3 I2C Acknowledge (slave) Step 4 I C Write register address (master) Step 5 I2C Acknowledge (slave) Step 6 I2C Stop (master) 2 2 0 S 7 1 9 A 7 Addr 9 A 0 P 6 Addr 5 Addr 4 Addr 3 Addr 2 Addr 1 Addr 0 Addr 6 0 5 1 4 1 3 1 2 0 1 X 0 0 3. 15. 2. 2 Read Phase 2 Step 7 I C Start (master) Step 8 I2C slave address (master) Step 9 I2C Acknowledge (slave) Step 10 I2C Read data (slave) Step 11 (1) I2C Not Acknowledge (master) Step 12 I2C Stop (master) (1) 2 0 S 7 1 9 A 7 Data 9 A 0 P 6 Data 5 Data 4 Data 3 Data 2 Data 1 Data 0 Data 6 0 5 1 4 1 3 1 2 0 1 X 0 1 Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received. 26 Functional Description Submit Documentation Feedback Copyright © 2009­2010, Texas Instruments Incorporated TVP5151 www. ti. com SLES241B ­ SEPTEMBER 2009 ­ REVISED JUNE 2010 3. 15. 2. 3 I2C Timing Requirements The TVP5151 decoder requires delays in the I2C accesses to accommodate its internal processor's timing. In accordance with I2C specifications, the TVP5151 decoder holds the I2C clock line (SCL) low to indicate the wait period to the I2C master. If the I2C master is not designed to check for the I2C clock line held-low condition, then the maximum delays must always be inserted where required. These delays are of variable length; maximum delays are indicated in the following diagram: Normal register writing addresses 00h to 8Fh (addresses 90h to FFh do not require delays). Start Slave address (B8h) Ack Subaddress Ack Data (XXh) Ack Wait 64 µs Stop The 64-µs delay is for all registers that do not require a reinitialization. Delays may be more for some registers. 3. 16 Clock Circuits An internal line-locked PLL generates the system and pixel clocks. A 27. 000-MHz clock is required to drive the PLL. This may be input to the TVP5151 decoder on terminal 5 (XTAL1), or a crystal of 27. 000-MHz fundamental resonant frequency may be connected across terminals 5 and 6 (XTAL2). Figure 3-8 shows the reference clock configurations. For the example crystal circuit shown (a parallel-resonant crystal with 27. 000-MHz fundamental frequency), the external capacitors must have the following relationship: CL1 = CL2 = 2CL ­ CSTRAY where CSTRAY is the terminal capacitance with respect to ground, and CL is the crystal load capacitance specified by the crystal manufacturer. [. . . ] All products are sold subject to TI's terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. [. . . ]