User manual TRANSCEND 150X SECURE DIGITAL CARD QUICK INSTRUCTION GUIDE

[. . . ] In addition, some operations have a data token. Data transfers to/from the SD Memory Card are done in blocks. Data blocks always succeeded by CRC bits. Single and multiple block operations are defined. [. . . ] When the wide bus option is used, the data is transferred 4 bits at a time (refer to Figure 10). Start and end bits, as well as the CRC bits, are transmitted for every one of the DAT lines. CRC bits are calculated and checked for every DAT line individually. The CRC status response and Busy indica-tion will be sent by the card to the host on DAT0 only (DAT1-DAT3 during that period are don't care). Transcend Information Inc. 5 TS2GSD150 SPI bus 2GB 150x Secure Digital Card While the SD channel is based on command and data bit streams which are initiated by a start bit and terminated by a stop bit, the SPI channel is byte oriented. Every command or data block is built of 8-bit bytes and is byte aligned to the CS signal (i. e. the length is a multiple of 8 clock cycles). Similar to the SD protocol, the SPI messages consist of command, response and data-block tokens All communication between host and cards is controlled by the host (master). The host starts every bus transaction by asserting the CS signal low. The response behavior in the SPI mode differs from the SD mode in the following three aspects: · The selected card always responds to the command. · Two new (8 & 16 bit) response structure is used · When the card encounters a data retrieval problem, it will respond with an error response (which replaces the expected data block) rather than by a time-out as in the SD mode. In addition to the command response, every data block sent to the card during write operations will be responded with a special data response token. This register is not implemented Transcend Information Inc. 8 TS2GSD150 4. Relative Card Address Register (RCA) 2GB 150x Secure Digital Card The writable 16-bit relative card address register carries the card address assigned by the host during the card identification. This address is used for the addressed host-card communication after the card identification procedure. The default value of the RCA register is 0x0001. The value 0x0000 is reserved to set all cards into the Stand-by State with CMD7. In SD mode, the value of this register is generated by random number generator inside the card. Please reference to SD specification for detail information. 5. Card Specific Data Register (CSD) The Card-Specific Data register provides information on how to access the card contents. The CSD defines the data format, error correction type, maximum data access time, data transfer speed, whether the DSR register can be used etc. The programmable part of the register can be changed by CMD27. CSD bit [127:126] [125:120] [119:112] [111:104] [103:96] [95:84] [83:80] [79] [78] [77] [76] [75:74] [73:62] [61:59] [58:56] [55:53] [52:50] [49:47] [46] [45:39] [38:32] [31] [30:29] [28:26] [25:22] [21] [20:16] [15] Width 2 6 8 8 8 12 4 1 1 1 1 2 12 3 3 3 3 3 1 7 7 1 2 3 4 1 5 1 Name CSD structure Reserved Data read access-time 1 Data read access-time 2 Max. [. . . ] (*2)~(*4) This field is not a constant value. The value will be changed by different flash memory. 6. Extended CSD Register (EXT_CSD) The Extended CSD register defines the card properties and selected modes. The most significant 320 bytes are the Properties segment, which defines the card capabilities and cannot be modified by the host. [. . . ]