User manual TRANSCEND TS128MFLASHCP QUICK INSTRUCTION GUIDE

[. . . ] Global Wear Leveling ­ Advanced algorithm to enhance the Wear-Leveling Efficiency There are 3 main processes in global wear leveling approaches: (1) Record the block erase count and save in the wear-leveling table. (2) Find the static-block and save it in wear-leveling pointer. (3) Check the erase count when the block popped from spare pool. If the block erase count is bigger than WEARCNT, then swapped the static-block and over-count-block. [. . . ] The status bits are described as follows: Bit 7 (BUSY): the busy bit is set when the CompactFlash Storage Card has access to the command buffer and registers and the host is locked out from accessing the command register and buffer. No other bits in this register are valid when this bit is set to a 1. During the data transfer of DMA commands, the Card shall not assert DMARQ unless either the BUSY bit, the DRQ bit, or both are set to one. Bit 6 (RDY): RDY indicates whether the device is capable of performing CompactFlash Storage Card operations. This bit is cleared at power up and remains cleared until the CompactFlash Storage Card is ready to accept a command. Bit 5 (DWF): This bit, if set, indicates a write fault has occurred. Bit 4 (DSC): This bit is set when the CompactFlash Storage Card is ready. Bit 3 (DRQ): The Data Request is set when the CompactFlash Storage Card requires that information be transferred either to or from the host through the Data register. During the data transfer of DMA commands, the Card shall not assert DMARQ unless either the BUSY bit, the DRQ bit, or both are set to one. Bit 2 (CORR): This bit is set when a Correctable data error has been encountered and the data has been corrected. This condition does not terminate a multi-sector read operation. It is recommended that this register not be mapped into the host's I/O space because of potential conflicts on Bit 7. Bit 7: this bit is unknown. Implementation Note: Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller operating at the same addresses as the CompactFlash Storage Card. Following are some possible solutions to this problem for the PCMCIA implementation: 1) Locate the CompactFlash Storage Card at a non-conflicting address, i. e. Secondary address (377) or in an independently decoded Address Space when a Floppy Disk Controller is located at the Primary addresses. 2) Do not install a Floppy and a CompactFlash Storage Card in the system at the same time. 3) Implement a socket adapter that can be programmed to (conditionally) tri-state D7 of I/0 address 3F7h/377h when a CompactFlash Storage Card is installed and conversely to tristate D6-D0 of I/O address 3F7h/377h when a floppy controller is installed. 4) Do not use the CompactFlash Storage Card's Drive Address register. This may be accomplished by either a) If possible, program the host adapter to enable only I/O addresses 1F0h-1F7h, 3F6h (or 170h-177h, 176h) to the CompactFlash Storage Card or b) if provided use an additional Primary / Secondary configuration in the CompactFlash Storage Card which does not respond to accesses to I/O locations 3F7h and 377h. With either of these implementations, the host software shall not attempt to use information in the Drive Address Register. Bit 6 (-WTG): this bit is 0 when a write operation is in progress; otherwise, it is 1. Bit 5 (-HS3): this bit is the negation of bit 3 in the Drive/Head register. [. . . ] Bit 0-11: Maximum current This field contains the CompactFlash Storage Card's maximum current in mA. Word 162: Key Management Schemes Supported Bit 0: CPRM support If set to 1, the device supports CPRM Scheme (Content Protection for Recordable Media) If set to 0, the device does not support CPRM. Bits 1-15 are reserved for future additional Key Management schemes. Transcend Information Inc. 82 V1. 2 Transcend IIndustriiall CF Card Transcend ndustr a CF Card TS128M~16GCF200II TS128M~16GCF200 Word 163: CF Advanced True IDE Timing Mode Capabilities and Settings This word describes the capabilities and current settings for CFA defined advanced timing modes using the True IDE interface. The use of True IDE PIO Modes 5 and above or of Multiword DMA Modes 3 and above impose significant restrictions on the implementation of the host: Additional Requirements for CF Advanced Timing Modes. [. . . ]