User manual TRANSCEND TS512MCF80-P QUICK INSTRUCTION GUIDE

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Manual abstract: user guide TRANSCEND TS512MCF80-PQUICK INSTRUCTION GUIDE

Detailed instructions for use are in the User's Guide.

[. . . ] 3) The signal should be tied to VCC by the host. 4) The mode is required for CompactFlash Storage Cards. 5) The -CSEL signal is ignored by the card in PC Card modes. However, because it is not pulled upon the card in these modes, it should not be left floating by the host in PC Card modes. [. . . ] The bits are defined as follows: Bit 7: this bit is unknown. Implementation Note: Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller operating at the same addresses as the CompactFlash Storage Card. Following are some possible solutions to this problem for the PCMCIA implementation: 1) Locate the CompactFlash Storage Card at a non-conflicting address, i. e. Secondary address (377) or in an independently decoded Address Space when a Floppy Disk Controller is located at the Primary addresses. 2) Do not install a Floppy and a CompactFlash Storage Card in the system at the same time. 3) Implement a socket adapter that can be programmed to (conditionally) tri-state D7 of I/0 address 3F7h/377h when a CompactFlash Storage Card is installed and conversely to tristate D6-D0 of I/O address 3F7h/377h when a floppy controller is installed. 4) Do not use the CompactFlash Storage Card's Drive Address register. This may be accomplished by either a) If possible, program the host adapter to enable only I/O addresses 1F0h-1F7h, 3F6h (or 170h-177h, 176h) to the CompactFlash Storage Card or b) if provided use an additional Primary / Secondary configuration in the CompactFlash Storage Card which does not respond to accesses to I/O locations 3F7h and 377h. With either of these implementations, the host software shall not attempt to use information in the Drive Address Register. Bit 6 (-WTG): this bit is 0 when a write operation is in progress; otherwise, it is 1. Bit 5 (-HS3): this bit is the negation of bit 3 in the Drive/Head register. Transcend Information Inc. 42 V1. 7 TS32M~1GCF80 TS32M~1GCF80 Bit 4 (-HS2): this bit is the negation of bit 2 in the Drive/Head register. The parameter words in the buffer have the arrangement and meanings defined in Table as below. Hosts should not depend on Obsolete words in Identify Device containing 0. Table specifies each field in the data returned by the Identify Device Command. In Table as below, X indicates a numeric nibble value specific to the card and aaaa indicates an ASCII string specific to the particular drive. Word Address 0 1 2 3 4 5 6 7-8 9 10-19 20 21 22 23-26 27-46 47 48 49 50 Default Value 848Ah 0XXX XXXXh 0000h 00XXh 0000h 0000h XXXXh XXXXh XXXXh aaaa 0000h 0000h 0004h aaaa aaaa XXXXh 0000h XX00h 0000h Total Bytes 2 2 2 2 2 2 2 2 4 2 20 2 2 2 8 40 2 2 2 2 Data Field Type Information General configuration - signature for the CompactFlash 0 lash Storage Card General configuration ­ Bit Significant with ATA-4 definitions. Default number of cylinders Reserved Default number of heads Obsolete Obsolete Default number of sectors per track Number of sectors per card (Word 7 = MSW, Word 8 = LSW) Obsolete Serial number in ASCII (Right Justified) Obsolete Obsolete Number of ECC bytes passed on Read/Write Long Commands Firmware revision in ASCII. Big Endian Byte Order in Word Model number in ASCII (Left Justified) Big Endian Byte Order in Word Maximum number of sectors on Read/Write Multiple command Reserved Capabilities Reserved Transcend Information Inc. 48 V1. 7 TS32M~1GCF80 TS32M~1GCF80 Word Address 51 52 53 54 55 56 57-58 59 60-61 62 63 64 65 66 67 68 69-79 80-81 82-84 85-87 88 89 90 91 92-127 128 129-159 160 161 162 163 164 165-167 168-255 Default Value 0X00h 0000h 000Xh XXXXh XXXXh XXXXh XXXXh 01XXh XXXXh 0000h 0X0Xh 00XXh XXXXh XXXXh XXXXh XXXXh 0000h 0000h XXXXh XXXXh XXXXh XXXXh XXXXh XXXXh 0000h XXXXh 0000h XXXXh 0000h 0000h XXXXh XXXXh 0000h 0000h Total Bytes 2 2 2 2 2 2 4 2 4 2 2 2 2 2 2 2 20 4 6 6 2 2 2 2 72 2 64 2 2 2 2 2 6 158 Obsolete Field Validity Current numbers of cylinders Current numbers of heads Current sectors per track 80X CompactFlash Card Data Field Type Information PIO data transfer cycle timing mode Current capacity in sectors (LBAs)(Word 57 = LSW, Word 58 = MSW) Multiple sector setting Total number of sectors addressable in LBA Mode Reserved Multiword DMA transfer. In PC Card modes this value shall be 0h Advanced PIO modes supported Minimum Multiword DMA transfer cycle time per word. In PC Card modes this value shall be 0h Recommended Multiword DMA transfer cycle time. In PC Card modes this value shall be 0h Minimum PIO transfer cycle time without flow control Minimum PIO transfer cycle time with IORDY flow control Reserved Reserved ­ CF cards do not return an ATA version Features/command sets supported Features/command sets enabled Reserved Time required for Security erase unit completion Time required for Enhanced security erase unit completion Current Advanced power management value Reserved Security status Vendor unique bytes Power requirement description Reserved for assignment by the CFA Key management schemes supported CF Advanced True IDE Timing Mode Capability and Setting CF Advanced PC Card I/O and Memory Timing Mode Capability Reserved for assignment by the CFA Reserved Transcend Information Inc. 49 V1. 7 TS32M~1GCF80 TS32M~1GCF80 80X CompactFlash Card Word 0: General Configuration This field indicates the general characteristics of the device. When Word 0 of the Identify drive information is 848Ah then the device is a CompactFlash Storage Card and complies with the CFA specification and CFA command set. It is recommended that PCMCIA modes of operation report only the 848Ah value as they are always intended as removable devices. [. . . ] Errors encountered during Write Multiple commands are posted after the attempted writes of theblock or partial block transferred. The Write command ends with the sector in error, even if it is in the middle of a block. Subsequent blocks are not transferred in the event of an error. Interrupts are generated when DRQ is set at the beginning of each block or partial block. [. . . ]

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