User manual TRANSCEND TS8GDOM40V-S DATASHEET

[. . . ] Transcend 40-Piin IIDE Fllash Modulle Transcend 40-P n DE F ash Modu e TS128M ~ 16GDOM40V-S TS128M ~ 16GDOM40V-S Description With an IDE interface and strong data retention ability, 40-Pin IDE Flash Modules are ideal for use in the harsh environments where Industrial PCs, Set-Top Boxes, etc. are used. Features · · · · · · · · · · RoHS compliant products Storage Capacity: 128MB ~ 16GB Operating Voltage: 3. 3V ±5% or 5V ±10% Operating Temperature: 0°C ~ 70°C Endurance: 2, 000, 000 Program/Erase cycles MTBF: 1, 000, 000 hours Durability of Connector: 10, 000 times Fully compatible with devices and OS that support the IDE standard (pitch = 2. 54mm) Built-in ECC function assures high reliability of data transfer Supports up to Ultra DMA Mode 4 Supports PIO Mode 6 Support Wear-Leveling to extend product life Placement · · Dimensions Side A B C Millimeters 61. 00 ± 0. 40 27. 10 ± 0. 50 7. 10 ± 0. 20 Inches 2. 402 ± 0. 016 1. 067 ± 0. 020 0. 280 ± 0. 008 Transcend Information Inc. 1 Ver 1. 2 Transcend 40-Piin IIDE Fllash Modulle Transcend 40-P n DE F ash Modu e TS128M ~ 16GDOM40V-S TS128M ~ 16GDOM40V-S Pin Assignments Pin No. Pin Name IREQ IOIS16B HA1 PDIAGB HA0 HA2 CE1B CE2B DASPB GND Input Power The 40-Pin IDE Flash Module offers 2 ways to get input power, either via the small power cord or through Pin 20 of the IDE connector. If Pin 20 of the IDE connector is defined as NC (No Connect), then the 40-Pin IDE Flash Module must be directly connected to your system's power supply. [. . . ] The timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data Burst Timing Descriptions. The following steps shall occur in the order they are listed unless otherwise specifically allowed: (a) The device shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data burst has been transferred. (b) The device shall pause an Ultra DMA data burst by not generating DSTROBE edges. (c) NOTE - The host shall not immediately assert STOP to initiate Ultra DMA data burst termination when the device stops generating STROBE edges. If the device does not negate DMARQ, in order to initiate Ultra DMA data burst termination, the host shall negate -HDMARDY and wait tRP before asserting STOP. (d) The device shall resume an Ultra DMA data burst by generating a DSTROBE edge. ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH. NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM. Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions. Transcend Information Inc. 19 Ver 1. 2 Transcend 40-Piin IIDE Fllash Modulle Transcend 40-P n DE F ash Modu e TS128M ~ 16GDOM40V-S TS128M ~ 16GDOM40V-S Host Terminating an Ultra DMA Data-In Burst The host terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing diagram is shown in below: Ultra DMA Data-In Burst Host Termination Timing. The timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data Burst Timing Descriptions. The following steps shall occur in the order they are listed unless otherwise specifically allowed: (a) The host shall not initiate Ultra DMA data burst termination until at least one data word of an Ultra DMA data burst has been transferred. (b) The host shall initiate Ultra DMA data burst termination by negating -HDMARDY. The host shall continue to negate -HDMARDY until the Ultra DMA data burst is terminated. (c) The device shall stop generating DSTROBE edges within tRFS of the host negating -HDMARDY (d) While operating in Ultra DMA modes 2, 1, or 0 the host shall be prepared to receive zero, one or two additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the host shall be prepared to receive zero, one, two or three additional data words. The additional data words are a result of cable round trip delay and tRFS timing for the device. (e) The host shall assert STOP no sooner than tRP after negating -HDMARDY. The host shall not negate STOP again until after the Ultra DMA data burst is terminated. (f) The device shall negate DMARQ within tLI after the host has asserted STOP. The device shall not assert DMARQ again until after the Ultra DMA data burst is terminated. (g) If DSTROBE is negated, the device shall assert DSTROBE within tLI after the host has asserted STOP. [. . . ] HSTROBE shall remain asserted until the Ultra DMA data burst is terminated. (f) The host shall place the result of its CRC calculation on D[15:00] (see ATA specification Ultra DMA CRC Calculation). (g) The host shall negate -DMACK no sooner than tMLI after the host has asserted HSTROBE and STOP and the device has negated DMARQ and -DDMARDY, and no sooner than tDVS after placing the result of its CRC calculation on D[15:00]. (h) The device shall latch the host's CRC data from D[15:00] on the negating edge of -DMACK. [. . . ]