User manual TRANSCEND TS8GJFV60C

[. . . ] 2) The signal should be grounded by the host. 3) The signal should be tied to VCC by the host. 4) The mode is required for CompactFlash Storage Cards. 5) The -CSEL signal is ignored by the card in PC Card modes. [. . . ] Bit 4 (IDNF): the requested sector ID is in error or cannot be found. Bit 2 (Abort) This bit is set if the command has been aborted because of a CompactFlash Storage Card status condition: (Not Ready, Write Fault, etc. ) or when an invalid command has been issued. Bit 0 (AMNF) This bit is set in case of a general error. Transcend Information Inc. 54 V1. 5 TS8G~32GCF600 TS8G~32GCF600 600X CompactFlash Card Feature Register (Address - 1F1h[171h]; Offset 1, 0Dh Write Only) This register provides information regarding features of the CompactFlash Storage Card that the host can utilize. This register is also accessed in PC Card modes on data bits D15-D8 during a write operation to Offset 0 with -CE2 low and -CE1 high. Sector Count Register (Address - 1F2h[172h]; Offset 2) This register contains the numbers of sectors of data requested to be transferred on a read or write operation between the host and the CompactFlash Storage Card. If the value in this register is zero, a count of 256 sectors is specified. If the command was successful, this register is zero at command completion. If not successfully completed, the register contains the number of sectors that need to be transferred in order to complete the request. Sector Number (LBA 7-0) Register (Address - 1F3h[173h]; Offset 3) This register contains the starting sector number or bits 7-0 of the Logical Block Address (LBA) for any CompactFlash Storage Card data access for the subsequent command. 6. 1. 5. 5 Cylinder Low (LBA 15-8) Register (Address - 1F4h[174h]; Offset 4) This register contains the low order 8 bits of the starting cylinder address or bits 15-8 of the Logical Block Address. Cylinder High (LBA 23-16) Register (Address - 1F5h[175h]; Offset 5) This register contains the high order bits of the starting cylinder address or bits 23-16 of the Logical Block Address. It is Bit 24 in the Logical Block Address mode. Status & Alternate Status Registers (Address 1F7h[177h]&3F6h[376h]; Offsets 7 & Eh) These registers return the CompactFlash Storage Card status when read by the host. Reading the Status register does clear a pending interrupt while reading the Auxiliary Status register does not. The status bits are described as follows: Bit 7 (BUSY): the busy bit is set when the CompactFlash Storage Card has access to the command buffer and registers and the host is locked out from accessing the command register and buffer. No other bits in this register are valid when this bit is set to a 1. During the data transfer of DMA commands, the Card shall not assert DMARQ unless either the BUSY bit, the DRQ bit, or both are set to one. Bit 6 (RDY): RDY indicates whether the device is capable of performing CompactFlash Storage Card operations. This bit is cleared at power up and remains cleared until the CompactFlash Storage Card is ready to accept a command. Bit 5 (DWF): This bit, if set, indicates a write fault has occurred. Bit 4 (DSC): This bit is set when the CompactFlash Storage Card is ready. Bit 3 (DRQ): The Data Request is set when the CompactFlash Storage Card requires that information be transferred either to or from the host through the Data register. [. . . ] Value 0 1 2 3 4-7 Maximum PCMCIA IO timing mode Supported 255ns Cycle PCMCIA I/O Mode 120ns Cycle PCMCIA I/O Mode 100ns Cycle PCMCIA I/O Mode 80ns Cycle PCMCIA I/O Mode Reserved Bits 5-3: Maximum Memory timing mode supported Indicates the Maximum Memory timing mode supported by the card. Value Maximum Memory timing mode Supported 0 250ns Cycle Memory Mode Transcend Information Inc. 72 V1. 5 TS8G~32GCF600 TS8G~32GCF600 1 2 3 4-7 120ns Cycle Memory Mode 100ns Cycle Memory Mode 80ns Cycle Memory Mode Reserved 600X CompactFlash Card Bits 8-6: Maximum PC Card I/O UDMA timing mode supported Indicates the Maximum PC Card I/O UDMA timing mode supported by the card when bit 15 is set. Value 0 1 2 3 4 5 6 7 Maximum PC Card I/O UDMA timing mode Supported PC Card I/O UDMA mode 0 supported PC Card I/O UDMA mode 1 supported PC Card I/O UDMA mode 2 supported PC Card I/O UDMA mode 3 supported PC Card I/O UDMA mode 4 supported PC Card I/O UDMA mode 5 supported PC Card I/O UDMA mode 6 supported Reserved Bits 11-9: Maximum PC Card Memory UDMA timing mode supported Indicates the Maximum PC Card Memory UDMA timing mode supported by the card when bit 15 is set. Value 0 1 2 3 4 5 6 7 Maximum PC Card Memory UDMA timing mode Supported PC Card Memory UDMA mode 0 supported PC Card Memory UDMA mode 1 supported PC Card Memory UDMA mode 2 supported PC Card Memory UDMA mode 3 supported PC Card Memory UDMA mode 4 supported PC Card Memory UDMA mode 5 supported PC Card Memory UDMA mode 6 supported Reserved Bits 14-12: PC Card Memory or I/O UDMA timing mode selectedIndicates the PC Card Memory or I/O UDMA timing mode selected by the card. [. . . ]