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Manual abstract: user guide TRANSCEND TS8GSDHC4DATASHEET
Detailed instructions for use are in the User's Guide.
[. . . ] The host can determine CHOST and CBUS so that total bus capacitance is less than the card estimated capacitance load (CL=40 pF). The SD Memory Card guarantees its bus timing when total bus capacitance is less than maximum value of CL (40 pF).
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· Bus Signal Levels
4~16GB High Capacity Secure Digital Card
As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage.
To meet the requirements of the JEDEC specification JESD8-1A and JESD8-7, the card input and output voltages shall be within the following specified ranges for any VDD of the allowed voltage range:
Parameter
Output HIGH voltage Output LOW voltage Input HIGH voltage Input LOW voltage
Symbol
VOH VOL VIH VIL
Min.
0. 75* VDD
Max.
0. 125* VDD
Unit
V V V V
Remark
IOH = -100 µA @VDD min IOL = -100 µA @VDD min
0. 625* VDD VSS 0. 3
VDD + 0. 3 0. 25* VDD
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SDHC Card series
· Bus Timing
4~16GB High Capacity Secure Digital Card
Parameter
Clock frequency Data Transfer Mode Clock frequency Identification Mode Clock low time Clock high time Clock rise time Clock fall time Inputs CMD, DAT (referenced to CLK) Input set-up time Input hold time Outputs CMD, DAT (referenced to CLK)
Symbol
fPP fOD tWL tWH tTLH tTHL tISU tIH 6
Min
0 0(1)/100 10 10
Max.
25 400
Unit
MHz KHz ns ns
Remark
CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card)
Clock CLK (All values are referred to min (VIH) and max (VIL)
10 10 5 5
ns ns ns ns
Transcend Information Inc.
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SDHC Card series
Output Delay time during Data Transfer Mode tODLY 0
4~16GB High Capacity Secure Digital Card
14 ns CL 40 pF, (1 card)
CL 40 pF, (1 card) Output Delay time during Identification Mode tODLY 0 50 ns (1) 0 Hz means to stop the clock. The given minimum frequency range is for cases were continues clock is required
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Ver 1. 0
SDHC Card series
· Bus Timing (High Speed Mode)
4~16GB High Capacity Secure Digital Card
Parameter
Clock frequency Data Transfer Mode Clock low time Clock high time Clock rise time Clock fall time Inputs CMD, DAT (referenced to CLK) Input set-up time Input hold time Outputs CMD, DAT (referenced to CLK)
Symbol
fPP tWL tWH tTLH tTHL tISU tIH
Min
0 7 7
Max.
50
Unit
MHz ns ns
Remark
CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card) CCARD 10 pF, (1 card)
Clock CLK (All values are referred to min (VIH) and max (VIL)
3 3 6 2
ns ns ns ns
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Ver 1. 0
SDHC Card series
Output Delay time during Data Transfer Mode Output Hold time
1
4~16GB High Capacity Secure Digital Card
tODLY tOH 2. 5 40 14 ns ns pF CL 40 pF, (1 card) CL 40 pF, (1 card) (1 card)
Total System capacitance for each line CL 1) In order to satisfy severe timing, host shall drive only one card.
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SDHC Card series
Reliability and Durability
Temperature Operation: -25° / 85° C C
4~16GB High Capacity Secure Digital Card
Storage: -40° (168h) / 85° (500h) C C Junction temperature: max. 95° C Moisture and corrosion Operation: 25° / 95% rel. [. . . ] CID Register
The Card IDentification (CID) register is 128 bits wide. It contains the card identification information used during the card identification phase. Every individual flash card shall have a unique identification number. The structure of the CID register is defined in the following paragraphs:
· MID
An 8-bit binary number that identifies the card manufacturer. The MID number is controlled, defined, and allocated to a SD Memory Card manufacturer by the SD-3C, LLC. This procedure is established to ensure uniqueness of the CID register.
· OID
A 2-character ASCII string that identifies the card OEM and/or the card contents (when used as a distribution media either on ROM or FLASH cards). The OID number is controlled, defined, and allocated to a SD Memory Card manufacturer by the SD-3C, LLC. This procedure is established to ensure uniqueness of the CID register.
Note: SD-3C, LLC licenses companies that wish to manufacture and/or sell SD Memory Cards, including but not limited to flash memory, ROM, OTP, RAM, and SDIO Combo Cards. SD-3C, LLC is a limited liability company established by Matsushita Electric Industrial Co. Ltd. , SanDisk Corporation and Toshiba Corporation.
· PNM
The product name is a string, 5 ASCII characters long.
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· PRV
4~16GB High Capacity Secure Digital Card
The product revision is composed of two Binary Coded Decimal (BCD) digits, four bits each, representing an "n. m" revision number. The "n" is the most significant nibble and "m" is the least significant nibble. As an example, the PRV binary value field for product revision "6. 2" will be: 0110 0010
· PSN
The Serial Number is 32 bits of binary number.
· MDT
The manufacturing date composed of two hexadecimal digits, one is 8 bit representing the year(y) and the other is four bits representing the month(m). The "m" field [11:8] is the month code. The "y" field [19:12] is the year code. As an example, the binary value of the Date field for production date "April 2001" will be: 00000001 0100.
· CRC
CRC7 checksum (7 bits).
3. CSD Register
Table 5-16 shows Definition of the CSD for the High Capacity SD Memory Card (CSD Version 2. 0). The following sections describe the CSD fields and the relevant data types for the High Capacity SD Memory Card. CSD Version 2. 0 is applied to only the High Capacity SD Memory Card. The field name in parenthesis is set to fixed value and indicates that the host is not necessary to refer these fields. The fixed values enables host, which refers to these fields, to keep compatibility to CSD Version 1. 0. If set, a driver stage register (DSR)must be implemented also.
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Ver 1. 0
SDHC Card series
4~16GB High Capacity Secure Digital Card
· C_SIZE
This field is expanded to 22 bits and can indicate up to 2 TBytes (It is the same as the maximum memory space specified by a 32-bit block address. ) This parameter is used to calculate the user data area capacity in the SD memory card (not include the protected area). The user data area capacity is calculated from C_SIZE as follows: memory capacity = (C_SIZE+1) * 512K byte As the maximum capacity of the Physical Layer Specification Version 2. 00 is 32 GB, the upper 6 bits of this field shall be set to 0.
· ERASE_BLK_EN
This field is fixed to 1, which means the host can erase one or multiple units of 512 bytes.
· SECTOR_SIZE
This field is fixed to 7Fh, which indicates 64 KBytes. [. . . ] The default value of the DSR register
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SDHC Card series
is 0x404.
4~16GB High Capacity Secure Digital Card
6. SCR Register
In addition to the CSD register there is another configuration register that named - SD CARD Configuration Register (SCR). SCR provides information on SD Memory Card's special features that were configured into the given card. This register shall be set in the factory by the SD Memory Card manufacturer. [. . . ]
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