User manual TYAN TITAN TURBO PLUS ATX

[. . . ] Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Icons. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Hardware Specifications/Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Software Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Technical Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Returning Merchandise for Service. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2. [. . . ] However, for some older PCI cards, you do. Enabling this function allows the system to assign an IRQ. OS select for DRAM > 64 MB If you are using IBM OS/2, and more than 64MB of memory, you must Enable this field. Video BIOS Shadow This function allows BIOS to "shadow" firmware-to copy it from ROM into the system RAM. Once there, the CPU can read the firmware through the 16-bit or 32-bit DRAM BUS. Firmware that is not shadowed is read through the 8-bit X BUS. Shadowing improves the performance of the system BIOS and ROM firmware for expansion peripherals, but reduces the amount of high memory available for loading device drivers. Rather than shadowing all the available memory sections at once, you should Enable shadowing of each memory section independently, to see how it affects performance. BIOS 35 Chapter 4 Chipset Features Setup ROM PCI/ISA BIOS (2A59IT5A) CHIPSET SETUP UTILITY AWARD SOFTWARE, INC. Pipeline Cache Timing : Faster Chipset NA# Asserted : Enabled Mem. (MA/RAS) : Auto DRAM Leadoff Timing : 10/6/4 DRAM Refresh Rate : 15. 6 us DRAM Read Burst (EDO/FP) : x333/x444 CPU Warning Temperature : Disabled DRAM Write Burst Timing : x333 : 5C/ 95° 3° F Current CPU Temperature Fast EDO Lead Off : Disabled Refresh RAS# Assertion : 5 Clks Fast RAS To CAS delay :3 DRAM Page Idle Timer : 2 Clks DRAM Enhanced Paging : Enabled Fast MA to RAS# delay : 2 Clks ESC : Quit éêè ç : Select Item SDRAM(CAS Lat/RAS-to-CAS) : 3/3 F1 : Help PU/PD/+/- : Modify SDRAM Speculative Read : Disabled F5 : Old Values (Shift)F2 : Color System BIOS Cacheable : Disabled F6 : Load BIOS Defaults Video BIOS Cacheable : Disabled F7 : Load Setup Defaults 8 Bit I/O Recovery Time : NA 16 Bit I/O Recover Time : NA Memory Hole at 15M-16M : Disabled PCI 2. 1 Compliance : Disabled Auto Configuration DRAM Timing : Enabled : 70ns Auto Configuration This function selects the optimal values for your chipset parameters. If Disabled, the chipset parameters will revert to setup information stored in CMOS. When Auto Configuration is Enabled, many of the options below will not be available. DRAM Timing The value in this field is determined by the performance parameters of the installed DRAM chips. Unless you install new memory that has a different performance rating than the factory DRAMs, you should not alter this field. DRAM Leadoff Timing Selects the combination of CPU clocks the DRAM on your board requires before each read from or write to the memory. Beware: changing the value from the setting determined by the board designer for the installed DRAM may cause memory errors. 36 DRAM Read Burst (EDO/FP) Sets the timing for reads from EDO (Extended Data Output) or FP[M] (Fast Page Mode) memory. The lower you set the timing numbers, the faster the system will address the memory. Selecting timing numbers lower than the installed DRAM is able to support can result in memory errors. DRAM Write Burst Timing Sets the timing for writes to memory. As above, the lower the timing values, the faster the system will address the memory. Note that selecting timing numbers lower than the installed DRAM is able to support can result in memory errors. Fast EDO Leadoff Unless you have EDO DRAMS in a synchronous cache or cacheless system, select Disabled. Enabling will cause a 1-HCLK pull-in for all read leadoff latencies for EDO DRAMs (i. e. , page hits, page misses, and row misses). [. . . ] If it is, initializes mouse and installs interrupt vectors. Programs chipset registers with Setup values. Displays whether or not virus protection is enabled or disabled. Initializes floppy disk drive controller and any drives. [. . . ]