User manual TYAN TOMCAT I II

[. . . ] Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. 2 Hardware Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1. 3 Software Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1. 4 Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] The controls for this screen are the same as the previous screen. The Chipset Features Screen ROM ISA BIOS CHIPSET SETUP UTILITY AWARD SOFTWARE, INC. DRAM RAS# Precharge Time DRAM R/W Leadoff Timing Fast RAS# To CAS# Delay DRAM Read Burst Timing DRAM Write Burst Timing DRAM Speculative Leadoff Turn-Around Insertion System BIOS Cacheable Video BIOS Cacheable 8 bit I/O Recovery Time 16 bit I/O Recovery Time Memory Hole at 15M/16M IDE Block Mode IDE Primary Master PIO IDE Primary Slave PIO IDE Secondary Master PIO IDE Secondary Slave PIO On-Chip Primary PCI IDE On-Chip Secondary PCI IDE :4 :7/6 :3 :x4444 :x4444 :Disabled :Disabled :Enabled :Enabled :1 :1 :Disabled :Disabled :Auto :Auto :Auto :Auto :Enabled :Enabled PCI Slot IDE 2nd Channel Peer Concurrency Chipset Special Features DRAM ECC/Parity Select Onboard FDC Controller Onboard Serial Port 1 Onboard Serial Port 2 Onboard Parallel Port Parallel Port Mode :Enabled :Disabled :Disabled :Parity :Enabled :Com1/3F8 :Com2/2F8 :378/IRQ7 :Normal ESC :Quit F1 F5 F6 F7 :Select Item :Help PU/PD/+/- :Modify :Old Values (Shift)F2 :Color :Load BIOS Defaults :Load Setup Defaults S1562-001-01 33 w Chipset Features The DRAM timings can be altered from the default to optimize system performance. Be aware though that these settings are sensitive to the type and speed of DRAMs being used and can cause lockups or data lost if set incorrectly. The default settings should work with most DRAMs. w DRAM RAS# Precharge Time DRAM must continually be refreshed or it will lose its data. Normally, DRAM is refreshed entirely as the result of a single request. This option allows you to determine the number of CPU clocks allocated for the Row Address Strobe to accumulate its charge before the DRAM is refreshed. If insufficient time is allowed, refresh may be incomplete and data will be lost. A lower setting may increase performance. w DRAM R/W Leadoff Timing This sets the number of CPU clocks allowed before reads and writes to DRAM are performed. The default of 8/7 would set the leadoff timing for reads to eight clocks and writes to seven clocks. A lower setting may increase performance. w DRAM RAS to CAS Delay When DRAM is refreshed, both rows and columns are addressed separately. This option allows you to determine the timing of the transition from Row Address Strobe (RAS) to Column Address Strobe(CAS). A lower setting may increase performance. w DRAM Read/Write Burst Timing This sets the timing for Burst mode reads from DRAM. Burst read and write requests are generated by the CPU in four separate parts. The "x" is the leadoff cycle and is determined by the chipset and the memory timing. The remaining four numbers is the actual data cycles. The lower the timing numbers, the faster the system will address memory. The default for read burst timing is x4444. [. . . ] A62AW10. BIN and confirm that you want to program the BIOS. The utility will then `Blank', `Erase', and then `Program' the flash memory on the mainboard with the new BIOS file. You should choose "yes" to save the original system BIOS to a floppy diskette before you program the new BIOS. This leaves you with a backup of your original BIOS in case you need to reinstall it. [. . . ]