User manual TYAN TOMCAT IIIS D

[. . . ] Revision 1. 0 Single S1563S/Dual S1563D Pentium Class 430 HX 75MHz thru 200MHz PCI-ISA System Board User's Manual Table Of Contents 1. Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. 2 Hardware Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1. 3 Software Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1. 4 Environment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] w Video BIOS Shadow It determines whether Video BIOS will be copied to RAM, however, it is an optional chipset design. Default is Enabled. 4. 7 Chipset Features Setup This screen controls the settings for the board's chip set. The controls for this screen are the same as the previous screen. The Chipset Features Screen ROM ISA BIOS CHIPSET SETUP UTILITY AWARD SOFTWARE, INC. Auto Configuration DRAM Timing DRAM RAS# Precharge Time DRAM R/W Leadoff Timing Fast RAS# To CAS# Delay DRAM Read Burst Timing DRAM Write Burst Timing Turbo Read Leadoff DRAM Speculative Leadoff Turn-Around Insertion ISA Clock System BIOS Cacheable Video BIOS Cacheable 8 bit I/O Recovery Time 16 bit I/O Recovery Time Memory Hole at 15M/16M Peer Concurrency Chipset Special Features DRAM ECC/Parity Select :Disabled :70ns :4 :7/6 :3 :x4444 :x4444 :Disabled :Disabled :Disabled :PCILK/4 :Enabled :Enabled :1 :1 :Disabled :Enabled :Enabled :Parity Memory Parity/ECC Check Single Bit Error Report L2 Cache Cacheable Size Chipset NA# Asserted Pipline Cache Timing :Disabled :Disabled :64MB :Enabled :Faster ESC :Quit F1 F5 F6 F7 :Select Item :Help PU/PD/+/- :Modify :Old Values (Shift)F2 :Color :Load BIOS Defaults :Load Setup Defaults S1563-001-01 www. tyan. com 34 w Chipset Features The DRAM timings can be altered from the default to optimize system performance. Be aware though that these settings are sensitive to the type and speed of DRAMs being used and can cause lockups or data lost if set incorrectly. The default settings should work with most DRAMs. w DRAM RAS# Precharge Time DRAM must continually be refreshed or it will lose its data. Normally, DRAM is refreshed entirely as the result of a single request. This option allows you to determine the number of CPU clocks allocated for the Row Address Strobe to accumulate its charge before the DRAM is refreshed. If insufficient time is allowed, refresh may be incomplete and data will be lost. A lower setting may increase performance. w DRAM R/W Leadoff Timing This sets the number of CPU clocks allowed before reads and writes to DRAM are performed. The default of 8/7 would set the leadoff timing for reads to eight clocks and writes to seven clocks. A lower setting may increase performance. w DRAM RAS to CAS Delay When DRAM is refreshed, both rows and columns are addressed separately. This option allows you to determine the timing of the transition from Row Address Strobe (RAS) to Column Address Strobe(CAS). A lower setting may increase performance. w DRAM Read/Write Burst Timing This sets the timing for Burst mode reads from DRAM. Burst read and write requests are generated by the CPU in four separate parts. The "x" is the leadoff cycle and is determined by the chipset and the memory timing. The remaining four numbers is the actual data cycles. [. . . ] Make sure the CPU is running in `real mode'. FMW will not run if the CPU is operating in a protected or virtual mode. This means that you can not run it with Windows running or with any memory manager software. You must disable any memory manager first. [. . . ]