User manual TYAN TOMCAT IVS D

[. . . ] Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. 2 Hardware Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1. 3 Software Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Board Installation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2. 1 Unpacking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . [. . . ] A lower setting may increase performance. w DRAM R/W Leadoff Timing This sets the number of CPU clocks allowed before reads and writes to DRAM are performed. The default of 8/7 would set the leadoff timing for reads to eight clocks and writes to seven clocks. A lower setting may increase performance. w DRAM RAS to CAS Delay When DRAM is refreshed, both rows and columns are addressed separately. This option allows you to determine the timing of the transition from Row Address Strobe (RAS) to Column Address Strobe(CAS). A lower setting may increase performance. w DRAM Read/Write Burst Timing This sets the timing for Burst mode reads from DRAM. Burst read and write requests are generated by the CPU in four separate parts. The "x" is the leadoff cycle and is determined by the chipset and the memory timing. The remaining four numbers is the actual data cycles. The lower the timing numbers, the faster the system will address memory. The default for read burst timing is x4444. The default for write burst timing is x4444. S1564-001-01 www. tyan. com 34 w Speculative Leadoff The 430HX chipset is capable of allowing a DRAM read request to be generated slightly before the address has been fully decoded. More simply, the CPU will issue a read request and included with this request is the place(address) in memory where the desired data is to be found. This request is received by the DRAM controller. When enabled, the controller will issue the read command slightly before it has finished determining the address. w Turn-Around Insertion When this is enabled, the chipset will insert one extra clock to the turn-around of back to back DRAM cycles. w System BIOS Cacheable When enabled, accesses to the system BIOS ROM addressed at F0000H-FFFFFH are cached. Enable this for best performance under DOS/Windows or Windows95. When using operating systems that do not access the BIOS (Unix, OS/2, NT, etc. . . ) this setting can be disabled. w Video BIOS Cacheable As with caching the system BIOS above, enabling the Video BIOS cache will cause access to the video BOS addressed at C0000h to C7FFFFh to be cached. [. . . ] This leaves you with a backup of your original BIOS in case you need to reinstall it. If you can not sucessfully program the BIOS file for whatever reason, re-install you original BIOS from the backup file. W arning: If you do not successfully install a complete BIOS file in the flash memory on the Mainboard, your system may not be able to boot. If this happens, it will require service by your system vendor. [. . . ]