User manual VIA TECHNOLOGIES VT82885

[. . . ] VT82885 VIA Technologies, Inc. Real Time Clock electrical characteristics, bus timing and pin descriptions follows. FEATURES · Drop-in replacement for IBM AT computer clock/calendar. · Pin configuration closely matches the DS12887, DS12885and DS12885Q · Counts seconds, minutes, hours, days, day of the week, date, month, and year with leap year compensation · Binary or BCD representation of time, calendar and alarm · 12- or 24-hour clock with AM and PM in 12-hour mode · Daylight Savings Time option · Intel bus timing · Multiplex bus for pin efficiency · Interfaced with software as 128 RAM locations - 14 bytes of clock and control registers - 114 bytes of general purpose RAM · Programmable square wave output signal · Bus-compatible interrupt signals (IRQ#) · Three interrpts are separately softwaremaskable and testable - Times-of-day alarm once/second to once/day - Periodic rates from 122 µs to 500 ms - End of clock update cycle · Optional 28-pin PLCC surface mount package DESCRIPTION The VT82885 Real Time Clock is designed to be a direct replacement for the DS12885. The VT82885 is identical in form, fit and function to the DS12885. It has 114 bytes of general purpose RAM. [. . . ] These flag bits are set independent of the state of the corresponding enable bit in Register B. The flag bit can be used in a polling mode without enabling the corresponding enable bits. The interrupt flag bit is a status bit which software can interrogate as necessary. When the flag is set, an indication is given to software that an interrupt event has occurred since the flag bit was last read. ; however, care should be taken when using the flag bits as they are cleared each time Register C is read. Double latching is included with Register C so that bits which are set remain stable throughout the read cycle. All bits which are set (high) are cleared when read and new interrupts which are pending Real Time Clock during the read cycle are held until after the cycle is completed. One, two, or three bits can be set when reading Register C. Each utilized flag bit should be examined when read to ensure that no interrupts are lost. The second flag bit usage method is with fully enabled interrupts. When an interrupt flag bit is set and the corresponding interrupt enable bit is also set, the IRQ# pin is asserted low. IRQ# is asserted as long as at least one of three interrupt sources has its flag and enable bits both set. The IRQF bit in Register C is a one whenever the IRQ# pin is being driven low. Determination that the RTC initiated an interrupt is accom-plished by reading Register C. A logic one in bit 7 (IRQF bit) indicates that one or more interrupts have been initiated by the VT82885. The act of reading Register C clears all active flag bits and the IRQF bit. OSCILLATOR CONTROL BITS The VT82885's internal oscillator can be turned on and off as required. A pattern of 010 in bits 4 through 6 of Register A will turn the oscillator on and enable the countdown chain. A pattern of 11X will turn the oscillator on, but holds the countdown chain of the oscillator in reset. All other combinations of bits 4 through 6 keep the oscillator off. SQUARE WAVE OUTPUT SELECTION Thirteen of the 15 divider taps are made available to a 1-of-15 selector, as shown in the block diagram of Figure 1. The first purpose of selecting a divider tap is to generate a square wave output signal on the SQW pin. The PS0-RS3 bits in Register A establish the square wave output frequency. [. . . ] The RS3 through RS0 bits establish the periodic rate. PF is set to a one independent of the state of the PIE bit. When both PF and PIE are ones, the IRQ# signal is active and will set the IRQF bit. The PF bit is cleared by a RESET# or a software read of Register C. [. . . ]